| Patent application number | Description | Published |
|---|
| 20080200031 | Method of fabricating gate electrode having polysilicon film and wiring metal film - A method of forming a gate electrode of a semiconductor device according to example embodiments that may include forming a polysilicon film on a semiconductor substrate. An interface control layer may be formed on the polysilicon film by repeating a unit cycle a plurality of times. The unit cycle may include forming an interface metal film and nitriding an upper surface portion of the interface metal film to form an interface metal nitride film on an upper surface portion of the interface metal film. A wiring metal film may be formed on the interface control layer. | 08-21-2008 |
| 20080211038 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating a semiconductor device includes forming a preliminary gate pattern on a semiconductor substrate. The preliminary gate pattern includes a gate oxide pattern, a conductive pattern, and a sacrificial insulating pattern. The method further includes forming spacers on opposite sidewalls of the preliminary gate pattern, forming an interlayer dielectric pattern to expose the sacrificial insulating pattern, removing the sacrificial insulating pattern to form an opening to expose the conductive pattern, transforming the conductive pattern into a metal silicide layer and forming a metal barrier pattern along an inner profile of the opening and a metal conductive pattern to fill the opening including the metal barrier pattern. The metal silicide layer and the metal conductive pattern constitute a gate electrode. | 09-04-2008 |
| 20080214012 | Apparatus and method for fabricating semiconductor devices and substrates - An apparatus and method for fabricating semiconductor devices may increase reliability of the semiconductor devices by decreasing generation of particles and enhancing operation efficiency by decreasing the number of cleanings. The apparatus may include a chamber having a cover plate, susceptors for securely placing semiconductor substrates within the chamber, shower heads located on the cover plate to supply reaction gases into the chamber, and a curtain gas line connected to the cover plate to supply heated curtain gases between the shower heads. | 09-04-2008 |
| 20080274610 | METHODS OF FORMING A SEMICONDUCTOR DEVICE INCLUDING A DIFFUSION BARRIER FILM - Methods of forming a semiconductor device that includes a diffusion barrier film are provided. The diffusion barrier film includes a metal nitride formed by using a MOCVD process and partially treated with a plasma treatment. Thus, a specific resistance of the diffusion barrier film can be decreased, and the diffusion barrier film may have distinguished barrier characteristics. | 11-06-2008 |
| 20080296696 | Semiconductor Devices Including Doped Metal Silicide Patterns and Related Methods of Forming Such Devices - Provided are a semiconductor device and a method of forming the same. The method includes forming an interlayer dielectric on a semiconductor substrate, forming a contact hole in the interlayer dielectric to expose the semiconductor substrate, forming a metal pattern including a dopant on the exposed semiconductor substrate, and performing a heat treatment process to react the semiconductor substrate with the metal pattern to form a metal silicide pattern. The heat treatment process includes diffuses the dopant into the semiconductor substrate. | 12-04-2008 |
| 20080318421 | METHODS OF FORMING FILMS OF A SEMICONDUCTOR DEVICE - There is provided a method of forming a film of a semiconductor device. The method includes a step of adsorbing a liquefied metal ion source on the substrate; rinsing the substrate to remove any liquefied metal ion source that is not adsorbed to the substrate; depositing a metal layer on the substrate by reducing the liquefied metal ion source that is adsorbed on the substrate with a liquefied reducing agent; and rinsing the substrate to remove the remaining liquefied reducing agent and any reaction residual. | 12-25-2008 |
| 20090011583 | Method of manufacturing a semiconductor device - A gate structure is formed on a substrate. An insulating interlayer is formed covering the gate structure. The substrate is heat treated while exposing a surface of the insulating interlayer to a hydrogen gas atmosphere. A silicon nitride layer is formed directly on the interlayer insulating layer after the heat treatment and a metal wiring is formed on the insulating interlayer. The metal wiring may include copper. Heat treating the substrate while exposing a surface of the interlayer insulating layer to a hydrogen gas atmosphere may be preceded by forming a plug through the first insulating interlayer that contacts the substrate, and the metal wiring may be electrically connected to the plug. The plug may include tungsten. | 01-08-2009 |
| 20090014879 | Semiconductor device and method of manufacturing the same - In a method of forming a wiring structure for a semiconductor device, an insulation layer is formed on a semiconductor substrate on which a plurality of conductive structures is positioned. An upper surface of the insulation layer is planarized and spaces between the conductive structures are filled with the insulation layer. The insulation layer is partially removed from the substrate to form at least one opening through which the substrate is partially exposed. A residual metal layer is formed on a bottom and a lower portion of the sidewall of the at least one opening and a metal nitride layer is formed on the residual metal layer and an upper sidewall of the opening with a metal material. Accordingly, an upper portion of the barrier layer can be prevented from being removed in a planarization process for forming the metal plug. | 01-15-2009 |
| 20090035941 | METHODS AND APPARATUS FOR MANUFACTURING A SEMICONDUCTOR DEVICE IN A PROCESSING CHAMBER - An apparatus for manufacturing a semiconductor device includes a process chamber configured to perform a plurality of different processes on a substrate. A gas supply unit is configured to supply at least one process gas to the process chamber. At least one upper electrode unit is positioned at an upper portion of the process chamber. At least one lower electrode unit is opposite the upper electrode unit and configured to support a substrate thereon. A driving member is connected to at least one of the lower electrode unit and the upper electrode unit and is configured to move the lower electrode unit and/or the upper electrode unit to control a distance between the upper and the lower electrode units. A power supply unit is configured to apply a first power to the upper electrode unit and to apply a second power to the lower electrode unit. | 02-05-2009 |
| 20090101984 | Semiconductor device having gate electrode including metal layer and method of manufacturing the same - A semiconductor device may include a gate dielectric film on a semiconductor substrate and/or a gate electrode. The gate electrode may include a first metal film, a first metal silicide film, and/or a conductive polysilicon film sequentially stacked on the gate dielectric film. | 04-23-2009 |
| 20090137117 | Method Forming Contact Plug for Semiconductor Device Using H2 Remote Plasma Treatment - Provided are methods of forming a contact plug of a semiconductor device. Methods of forming a contact plug of a semiconductor device may include forming an interlayer insulating layer on a semiconductor substrate on which a lower structure is formed, forming a contact hole in the interlayer insulating layer, the contact hole exposing the lower structure, and forming a W layer and then a WN layer to form a W/WN barrier layer in the contact hole. Methods may include H | 05-28-2009 |
| 20090166868 | Semiconductor devices including metal interconnections and methods of fabricating the same - A semiconductor device includes a first interlayer dielectric including a trench on a semiconductor layer, a mask pattern on the first interlayer dielectric, a first conductive pattern in the trench, and a second interlayer dielectric on the mask pattern. The second interlayer dielectric includes an opening over the first conductive pattern. A second conductive pattern is in the opening and is electrically connected to the first conductive pattern. The first conductive pattern has an upper surface lower than an upper surface of the mask pattern. | 07-02-2009 |
| 20090176124 | Bonding pad structure and semiconductor device including the bonding pad structure - A bonding pad structure for a semiconductor device includes a first lower metal layer beneath a second upper metal layer in a bonding region of the device. The lower metal layer is formed such that the metal of the lower metal layer is absent from the bonding region. As a result, if damage occurs to the structure during procedures such as probing or bonding at the bonding region, the lower metal is not exposed to the environment. Oxidation of the lower metal layer by exposure to the environment is prevented, thus improving reliability of the device. | 07-09-2009 |
| 20090189229 | Semiconductor devices and methods of fabricating the same - Provided are semiconductor devices and methods of fabricating the same, and more specifically, semiconductor devices having a W—Ni alloy thin layer that has a low resistance, and methods of fabricating the same. The semiconductor devices include the W—Ni alloy thin layer. The weight of Ni in the W—Ni alloy thin layer may be in a range from approximately 0.01 to approximately 5.0 wt % of the total weight of the W—Ni alloy thin layer. | 07-30-2009 |
| 20090191699 | METHODS FOR FORMING SILICIDE CONDUCTORS USING SUBSTRATE MASKING - A plurality of spaced-apart conductor structures is formed on a semiconductor substrate, each of the conductor structures including a conductive layer. Insulating spacers are formed on sidewalls of the conductor structures. An interlayer-insulating film that fills gaps between adjacent ones of the insulating spacers is formed. Portions of the interlayer-insulating layer are removed to expose upper surfaces of the conductive layers. Respective epilayers are grown on the respective exposed upper surfaces of the conductive layers and respective metal silicide layers are formed from the respective epilayers. | 07-30-2009 |
| 20090239368 | Methods of Forming an Oxide Layer and Methods of Forming a Gate Using the Same - An oxide layer is selectively formed on a layer including silicon by a plasma process using hydrogen gas and a gas including oxygen. The hydrogen gas is controlled to have a flow rate less than about 50 percent of an overall flow rate by adding helium gas to the plasma process. | 09-24-2009 |
| 20090267132 | GATE STRUCTURES IN SEMICONDUCTOR DEVICES - A gate structure includes an insulation layer on a substrate, a first conductive layer pattern on the insulation layer, a metal ohmic layer pattern on the first conductive layer pattern, a diffusion preventing layer pattern on the metal ohmic layer pattern, an amorphous layer pattern on the diffusion preventing layer pattern, and a second conductive layer pattern on the amorphous layer pattern. The gate structure may have a low sheet resistance and desired thermal stability. | 10-29-2009 |
| 20090298282 | Methods of Forming Interlayer Dielectrics Having Air Gaps - Methods of forming an interlayer dielectric having an air gap are provided including forming a first insulating layer on a semiconductor substrate. The first insulating layer defines a trench. A metal wire is formed in the trench such that the metal wire is recessed beneath an upper surface of the first insulating layer. A metal layer is formed on the metal wire, wherein the metal layer includes a capping layer portion filling the recess, a upper portion formed on the capping layer portion, and an overhang portion formed on the portion of the first insulating layer adjacent to the trench protruding sideward from the upper portion. The first insulating layer is removed and a second insulating layer is formed on the semiconductor substrate to cover the metal layer, whereby an air gap is formed below the overhang portion of the metal layer. A portion of the second insulating layer is removed to expose the upper portion of the metal layer. The upper portion and the overhang portion of the metal layer are removed. A third insulating layer is formed on the semiconductor substrate from which the upper portion and the overhang portion have been removed to maintain the air gap. | 12-03-2009 |
| 20090315091 | GATE STRUCTURE, AND SEMICONDUCTOR DEVICE HAVING A GATE STRUCTURE - A gate structure can include a polysilicon layer, a metal layer on the polysilicon layer, a metal silicide nitride layer on the metal layer and a silicon nitride mask on the metal silicide nitride layer | 12-24-2009 |
| 20090325371 | Methods of Forming Integrated Circuit Devices Having Stacked Gate Electrodes - A method of forming a gate electrode of a semiconductor device is provided, the method including: forming a plurality of stacked structures each comprising a tunnel dielectric layer, a first silicon layer for floating gates, an intergate dielectric layer, a second silicon layer for control gates, and a mask pattern, on a semiconductor substrate in the stated order; forming a first interlayer dielectric layer between the plurality of stacked structures so that a top surface of the mask pattern is exposed; selectively removing the mask pattern of which the top surface is exposed; forming a third silicon layer in an area from which the hard disk layer was removed, and forming a silicon layer comprising the third silicon layer and the second silicon layer; recessing the first interlayer dielectric layer so that an upper portion of the silicon layer protrudes over the he first interlayer dielectric layer; and forming a metal silicide layer on the upper portion of the silicon layer. | 12-31-2009 |
| 20100022086 | METHOD OF MANUFACTURING A METAL WIRING STRUCTURE - In a method of manufacturing a metal wiring structure, a first metal wiring and a first barrier layer are formed on a substrate, and the first barrier layer is nitridated. An insulating interlayer is formed on the substrate so as to extend over the first metal wiring and the first barrier layer. Part of the insulating interlayer is removed to form a hole exposing at least part of the first metal wiring and part of the first barrier layer. A nitidation plasma treatment is performed on the exposed portion of the first barrier layer. A second barrier layer is formed along the bottom and sides of the hole. A plug is formed on the second barrier layer to fill the hole. | 01-28-2010 |
| 20100029073 | Methods of Forming Integrated Circuit Devices Having Anisotropically-Oxidized Nitride Layers - Methods of forming integrated circuit devices include forming a gate electrode on a substrate and forming a nitride layer on a sidewall and upper surface of the gate electrode. The nitride layer is then anisotropically oxidized under conditions that cause a first portion of the nitride layer extending on the upper surface of the gate electrode to be more heavily oxidized relative to a second portion of the nitride layer extending on the sidewall of the gate electrode. A ratio of a thickness of an oxidized first portion of the nitride layer relative to a thickness of an oxidized second portion of the nitride layer may be in a range from about 3:1 to about 7:1. | 02-04-2010 |
| 20100105198 | Gate Electrode of semiconductor device and method of forming the same - A method of forming a gate electrode of a semiconductor device includes forming a first polysilicon layer in a peripheral circuit region of a substrate, forming a barrier layer on the first polysilicon layer, the barrier layer providing an ohmic contact, forming a stack structure including a tunneling insulation layer, an electric charge storing layer, and a blocking insulation layer in a memory cell region of the substrate, forming a second polysilicon layer on the barrier layer and the blocking insulation layer, and siliciding the second polysilicon layer and forming a silicide gate electrode. | 04-29-2010 |
| 20100112772 | Method of fabricating semiconductor device - A method of fabricating a semiconductor device includes: forming a first polysilicon layer having a first thickness in a peripheral circuit region formed on a substrate; forming a stack structure comprising a first tunneling insulating layer, a charge trap layer, and a blocking insulating layer in a memory cell region formed on the substrate; forming a second polysilicon layer having a second thickness that is less than the first thickness on the blocking insulating layer; and forming gate electrodes by siliciding the first and second polysilicon layers. | 05-06-2010 |
| 20100120211 | Methods of manufacturing Semiconductor Devices Including PMOS and NMOS Transistors Having Different Gate Structures - A semiconductor device may include a semiconductor substrate having first and second regions. A first gate structure on the first region of the semiconductor substrate may include a metal oxide dielectric layer on the first region of the semiconductor substrate and a first conductive layer on the metal oxide dielectric layer. First and second source/drain regions of a first conductivity type may be provided in the first region of the semiconductor substrate on opposite sides of the first gate structure. A second gate structure on the second region of the semiconductor substrate may include a silicon oxide based dielectric layer and a second conductive layer on the silicon oxide based dielectric layer. First and second source/drain regions of a second conductivity type may be provided in the second region of the semiconductor substrate on opposite sides of the second gate structure, wherein the first and second conductivity types are different. Related methods are also discussed. | 05-13-2010 |
| 20100151674 | Structures Electrically Connecting Aluminum and Copper Interconnections and Methods of Forming the Same - A structure and formation method for electrically connecting aluminum and copper interconnections stabilize a semiconductor metallization process using an inner shape electrically connecting the aluminum and copper interconnections. To this end, a copper interconnection is disposed on a semiconductor substrate. An interconnection induction layer and an interconnection insertion layer are sequentially formed on the copper interconnection to have a contact hole exposing the copper interconnection. An upper diameter of the contact hole may be formed to be larger than a lower diameter thereof. A barrier layer and an aluminum interconnection are filled in the contact hole. The aluminum interconnection is formed not to directly contact the copper interconnection through the contact hole. | 06-17-2010 |
| 20100181671 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor device can include an insulation layer on that is on a substrate on which a plurality of lower conductive structures are formed, where the insulation layer has an opening. A barrier layer is on a sidewall and a bottom of the opening of the insulation layer, where the barrier layer includes a first barrier layer in which a constituent of a first deoxidizing material is richer than a metal material in the first barrier layer and a second barrier layer in which a metal material in the second barrier layer is richer than a constituent of a second deoxidizing material. An interconnection is in the opening of which the sidewall and the bottom are covered with the barrier layer, the interconnection is electrically connected to the lower conductive structure. | 07-22-2010 |
| 20100184294 | Method of Manufacturing a Semiconductor Device - In a method of manufacturing a semiconductor device, a substrate is loaded to a process chamber having, unit process sections in which unit processes are performed, respectively. The unit processes are performed on the substrate independently from one another at the unit process sections under a respective process pressure. The substrate sequentially undergoes the unit processes at the respective unit process section of the process chamber. Cleaning processes are individually performed to the unit process sections, respectively, when the substrate is transferred from each of the unit process sections and no substrate is positioned at the unit process sections. Accordingly, the process defects of the process units may be sufficiently prevented and the operation period of the manufacturing apparatus is sufficiently elongated. | 07-22-2010 |
| 20100193902 | SEMICONDUCTOR DEVICE INCLUDING FUSE - Provided is a semiconductor device including a fuse, in which a insulating layer surrounding the fuse or metal wiring is prevented from being damaged due to the cut of a fuse, which can occur when a repair process is performed. The semiconductor device includes a conductive line formed on a semiconductor layer, a protective layer formed on the conductive line, one or more fuses that are electrically connected to the conductive line, and a fuse protective layer formed on the one or more fuses, and spaced apart from the protective layer. | 08-05-2010 |
| 20100210105 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE HAVING BURIED WIRING - A method of fabricating a semiconductor device can include forming a trench in a semiconductor substrate, forming a first conductive layer on a bottom surface and side surfaces of the trench, and selectively forming a second conductive layer on the first conductive layer to be buried in the trench. The second conductive layer may be formed selectively on the first conductive layer by using an electroless plating method or using a metal organic chemical vapor deposition (MOCVD) or an atomic layer deposition (ALD) method. | 08-19-2010 |
| 20100237504 | Methods of Fabricating Semiconductor Devices Having Conductive Wirings and Related Flash Memory Devices - A conductive wiring for a semiconductor device is provided including a semiconductor substrate and a plurality of lower conductive structures on the semiconductor substrate. An insulating layer is provided that electrically insulates the plurality of lower conductive structures from one another. A first insulation interlayer pattern is provided on the insulation layer. The first insulation interlayer pattern includes a contact plug that contacts the substrate through the insulation layer. An etch-stop layer is provided on the contact plug and the first insulation interlayer pattern. A second insulation interlayer pattern is provided on the etch-stop layer. The second insulation interlayer pattern includes a conductive line that is electrically connected to the contact plug. Related methods and flash memory devices are also provided. | 09-23-2010 |
| 20100240185 | Semiconductor device and method of manufacturing the same - A method of manufacturing a semiconductor device includes: forming a trench for forming buried type wires by etching a substrate; forming first and second oxidation layers on a bottom of the trench and a wall of the trench, respectively; removing a part of the first oxidation layer and the entire second oxidation layer; and forming the buried type wires on the wall of the trench by performing a silicide process on the wall of the trench from which the second oxidation layer is removed. As a result, the buried type wires are insulated from each other. | 09-23-2010 |
| 20110003455 | METHODS FOR FABRICATING IMPROVED GATE DIELECTRICS - Disclosed are a variety of methods for increasing the relative thickness in the peripheral or edge regions of gate dielectric patterns to suppress leakage through these regions. The methods provide alternatives to conventional GPDX processes and provide the improved leakage resistance without incurring the degree of increased gate electrode resistance associated with GPDX processes. Each of the methods includes forming a first opening to expose an active area region, forming an oxidation control region on the exposed portion and then forming a second opening whereby a peripheral region free of the oxidation control region is exposed for formation of a gate dielectric layer. The resulting gate dielectric layers are characterized by a thinner central region surrounded or bounded by a thicker peripheral region. | 01-06-2011 |
| 20110003476 | METHODS OF FORMING SEMICONDUCTOR DEVICES INCLUDING LANDING PADS FORMED BY ELECTROLESS PLATING - A semiconductor device in which an increase of contact resistance Rc between a metal contact and a plug due to misalignment between the metal contact and the plug can be reduced and the difficulty of a Cu filling process during the process of forming the plug may be reduced. The semiconductor device includes a substrate including an active area and a device isolation layer; a metal contact that is formed on the substrate and is electrically connected to the active area; a landing pad formed on the metal contact by electroless plating; and a plug that is formed on the landing pad and is electrically connected to the metal contact via the landing pad. | 01-06-2011 |
| 20110092060 | METHODS OF FORMING WIRING STRUCTURES - A semiconductor memory wiring method includes: receiving a substrate having a cell array region and a peripheral circuit region; depositing a first insulating layer on the substrate; forming a first contact plug in the cell array region, the first contact plug having a first conductive material extending through the first insulating layer; forming a first elongated conductive line at substantially the same time as forming the first contact plug, the first elongated conductive line having the first conductive material directly covering and integrated with the first contact plug; forming a second contact plug in the peripheral circuit region at substantially the same time as forming the first contact plug, the second contact plug having the first conductive material extending through the first insulating layer; and forming a second elongated conductive line at substantially the same time as forming the second contact plug, the second elongated conductive line having the first conductive material directly covering and integrated with the second contact plug. | 04-21-2011 |
| 20110108988 | VIA STRUCTURES AND SEMICONDUCTOR DEVICES HAVING THE VIA STRUCTURES - A via structure may include a first conductive pattern, a buffer pattern, and a second conductive pattern. The first conductive pattern may be on an inner wall of a first substrate and the inner wall may define a via hole passing at least partially through the first substrate. The buffer pattern may be on the first conductive pattern and the buffer pattern may partially fill the via hole. The second conductive pattern may be on a top surface of the buffer pattern in the via hole. | 05-12-2011 |
| 20110115051 | SEMICONDUCTOR DEVICES INCLUDING 3-D STRUCTURES WITH SUPPORT PAD STRUCTURES AND RELATED METHODS AND SYSTEMS - A semiconductor device may include a semiconductor substrate and a plurality of three-dimensional capacitors on the semiconductor substrate. Each of the plurality of three-dimensional capacitors may include a first three-dimensional electrode, a capacitor dielectric layer, and a second three-dimensional electrode with the first three-dimensional electrode between the capacitor dielectric layer and the semiconductor substrate and with the capacitor dielectric layer between the first and second three-dimensional electrodes. A plurality of capacitor support pads may be provided with each capacitor support pad being arranged between adjacent first three-dimensional electrodes of adjacent three-dimensional capacitors with portions of the capacitor dielectric layers between the capacitor support pads and the semiconductor substrate. Related methods and apparatuses are also discussed. | 05-19-2011 |
| 20110136332 | METHODS OF FORMING INTEGRATED CIRCUIT DEVICES WITH CRACK-RESISTANT FUSE STRUCTURES - A fuse base insulating region, for example, an insulating interlayer or a compensation region disposed in an insulating interlayer, is formed on a substrate. An etch stop layer is formed on the fuse base insulating region and forming an insulating interlayer having a lower dielectric constant than the first fuse base insulating region on the etch stop layer. A trench extending through the insulating interlayer and the etch stop layer and at least partially into the fuse base insulating region is formed. A fuse is formed in the trench. The fuse base insulating region may have a greater mechanical strength and/or density than the second insulating interlayer. | 06-09-2011 |
