| Patent application number | Description | Published |
|---|
| 20090026437 | Copper compatible chalcogenide phase change memory with adjustable threshold voltage - A phase change memory cell may include two or more stacked or unstacked series connected memory elements. The cell has a higher, adjustable threshold voltage. A copper diffusion plug may be provided within a pore over a copper line. By positioning the plug below the subsequent chalcogenide layer, the plug may be effective to block copper diffusion upwardly into the pore and into the chalcogenide material. Such diffusion may adversely affect the electrical characteristics of the chalcogenide layer. | 01-29-2009 |
| 20090196091 | Self-aligned phase change memory - A self-aligned phase change memory may be formed by blanket depositing a number of layers and then using patterning techniques to define the individual cells. In one embodiment, a layer of phase change material may be blanket deposited over a lower electrode material. The structure may then be patterned and etched to form a plurality of spaced, parallel elongate first strips. Those strips may then be covered with a filler material, planarized, and then patterned again in a transverse direction to form a plurality of transverse, spaced, parallel second strips. The resulting structure then has singulated phase change material with connections in at least one of the row or column direction. The singulated the phase change material is self-aligned to underlying and overlying electrodes. | 08-06-2009 |
| 20090244962 | Immunity of phase change material to disturb in the amorphous phase - Disturb from the reset to the set state may be reduced by creating an amorphous phase that is substantially free of crystal nuclei when programming the reset state in a phase change memory. In some embodiments, this can be achieved by using a current or a voltage to program that exceeds the threshold voltage of the phase change memory element, but does not exceed a safe current voltage which would cause a disturb. | 10-01-2009 |
| 20090302298 | Forming sublithographic phase change memory heaters - A phase change memory may be formed with a sublithographic heater by using a mask with a sidewall spacer to etch an opening in a dielectric layer. The opening then has a sublithographic lateral extent. The resulting via may be filled with a heater material to form a sublithographic heater. | 12-10-2009 |
| 20110128770 | STORED MULTI-BIT DATA CHARACTERIZED BY MULTIPLE-DIMENSIONAL MEMORY STATES - Subject matter disclosed herein relates to enhancing data storage density of a memory device. | 06-02-2011 |
| 20110134685 | Energy-efficient set write of phase change memory with switch - Embodiments of apparatus and methods for an energy efficient set write of phase change memory with switch are generally described herein. Other embodiments may be described and claimed. | 06-09-2011 |
| 20110147695 | FABRICATING CURRENT-CONFINING STRUCTURES IN PHASE CHANGE MEMORY SWITCH CELLS - In one or more embodiments, methods of fabricating current-confining stack structures in a phase change memory switch (PCMS) cell are provided. One embodiment shows a method of fabricating a PCMS cell with current in an upper chalcogenide confined in the row and column directions. In one embodiment, methods of fabricating a PCMS cell with sub-lithographic critical dimension memory chalcogenide are shown. In another embodiment, methods of fabricating a PCMS cell with sub-lithographic critical dimension middle electrode heaters are disclosed. | 06-23-2011 |
| 20110240943 | Immunity of Phase Change Material to Disturb in the Amorphous Phase - Disturb from the reset to the set state may be reduced by creating an amorphous phase that is substantially free of crystal nuclei when programming the reset state in a phase change memory. In some embodiments, this can be achieved by using a current or a voltage to program that exceeds the threshold voltage of the phase change memory element, but does not exceed a safe current voltage which would cause a disturb. | 10-06-2011 |
