Patent application number | Description | Published |
20080246158 | Method for Realizing a Nanometric Circuit Architecture Between Standard Electronic Components and Semiconductor Device Obtained with Said Method - A method for realizing a nanometric circuit architecture includes: realizing plural active areas on a semiconductor substrate; realizing on the substrate a seed layer of a first material; realizing a mask-spacer of a second material on the seed layer in a region comprised between the active areas; realizing a mask overlapping the mask-spacer and extending in a substantially perpendicular direction thereto; selectively removing the seed layer exposed on the substrate; selectively removing the mask and the mask-spacer obtaining a seed-spacer comprising a linear portion extending in that region and a portion substantially orthogonal thereto; realizing by MSPT from the seed-spacer an insulating spacer reproducing at least part of the profile of the seed-spacer realizing by MSPT a nano-wire of conductive material from the seed-spacer or insulating spacer, the nano-wire comprising a first portion at least partially extending in the region and a second portion contacting a respective active area. | 10-09-2008 |
20090003063 | METHOD AND DEVICE FOR DEMULTIPLEXING A CROSSBAR NON-VOLATILE MEMORY - A method and device demultiplex a crossbar non-volatile memory that includes a first array of row nano-wires and a second array of column nano-wires, which cross the row nano-wires at a plurality of cross-points, hosting plural memory cells. A first electrode and a second electrode respectively cross a modulated doping portion of the row nano-wires and a modulated doping portion of the column nano-wires. A first contact and a second contact respectively the row nano-wires and the column nano-wires. The first electrode and the second electrode are biased respectively with a first and a second adjustable voltage value that progressively switch one by one said memory cells from the OFF state to the ON state, and this state can be memorized. | 01-01-2009 |
20090020747 | METHOD FOR REALIZING A HOSTING STRUCTURE OF NANOMETRIC ELEMENTS - A nanometric device comprising a substrate; a plurality of conductive spacers of a conductive material, each conductive spacer being arranged on top of and transverse to the substrate, the conductive spacers including respective pairs of conductive spacers defining respective hosting seats each of less than 30 nm wide; and a plurality of nanometric elements respectively accommodated in the hosting seats. | 01-22-2009 |
20090154223 | METHOD AND DEVICE FOR DEMULTIPLEXING A CROSSBAR NON-VOLATILE MEMORY - A method and device demultiplex a crossbar non-volatile memory that includes a first array of row nano-wires and a second array of column nano-wires, which cross the row nano-wires at a plurality of cross-points, hosting plural memory cells. A first electrode and a second electrode respectively cross a modulated doping portion of the row nano-wires and a modulated doping portion of the column nano-wires. A first contact and a second contact respectively the row nano-wires and the column nano-wires. The first electrode and the second electrode are biased respectively with a first and a second adjustable voltage value that progressively switch one by one said memory cells from the OFF state to the ON state, and this state can be memorized. | 06-18-2009 |
20100019389 | ELECTRIC LINKAGE IN A SEMICONDUCTOR ELECTRONIC DEVICE BETWEEN A NANOMETRIC CIRCUIT ARCHITECTURE AND STANDARD ELECTRONIC COMPONENTS - A semiconductor electronic device that includes a semiconductor substrate having a top surface; a seed layer positioned on the substrate and having a notched wall extending transversely with respect to the substrate top surface, the wall defining a first recess extending into the seed layer with a height equal to a thickness of the seed layer; a first conductive nanowire in contact with the notched wall, the first conductive nanowire having a contact portion extending into the first recess and covering opposite sidewalls and a bottom of the first recess; a first insulating nanowire in contact with a sidewall of the first conductive nanowire; an insulating layer on the contact portion of the first conductive nanowire and having a first window substantially in correspondence with the contact portion of the first conductive nanowire; and a first conductive die on the insulating layer that includes a conductive contact extending into the first window and contacting the contact portion of the first conductive nanowire. | 01-28-2010 |
20120174954 | SEEBECK/PELTIER THERMOELECTRIC CONVERSION DEVICE EMPLOYING TREATED FILMS OF SEMICONDUCTING MATERIAL NOT REQUIRING NANOMETRIC DEFINITION - The disclosure relates to Seebeck/Peltier effect thermoelectric conversion devices and in particular devices made of stack of dielectric layers alternated to treated semiconducting layers even of large size, not requiring lithographic patterning in a nano-micrometric scale. | 07-12-2012 |
20120279542 | SEEBECK/PELTIER THERMOELECTRIC CONVERSION DEVICE EMPLOYING A STACK OF ALTERNATED NANOMETRIC LAYERS OF CONDUCTIVE AND DIELECTRIC MATERIAL AND FABRICATION PROCESS - A multilayered stack useful for constituting a Seebeck-Peltier effect electrically conductive septum with opposite hot-side and cold-side metallizations for connection to an electrical circuit, comprises a stacked succession of layers (Ci) of electrically conductive material alternated to dielectric oxide layers (Di) in form of a continuous film or of densely dispersed nano and sub-nano particles or clusters of particles of oxide; at least the electrically conductive layers having mean thickness ranging from 5 to 100 nm and surface irregularities at the interfaces with the dielectric oxide layers of mean peak-to-valley amplitude and mean periodicity comprised between 5 to 20 nm. | 11-08-2012 |
20130037070 | SEEBECK/PELTIER THERMOELECTRIC CONVERSION ELEMENT WITH PARALLEL NANOWIRES OF CONDUCTOR OR SEMICONDUCTOR MATERIAL ORGANIZED IN ROWS AND COLUMNS THROUGH AN INSULATING BODY AND PROCESS - A novel and effective structure of a stackable element (A | 02-14-2013 |
20150083178 | SEEBECK/PELTIER THERMOELECTRIC CONVERSION DEVICE HAVING PHONON CONFINEMENT LAYERS OF CRYSTALLINE SEMICONDUCTOR CONTAINING ANGSTROM-SIZED ORGANIC GROUPS AS SEMICONDUCTOR ATOMS SUBSTITUENTS WITHIN THE CRYSTAL LATTICE AND FABRICATION PROCESS - Significant phonon migration restraint is achieved within a relatively homogeneous polycrystalline doped semiconductor bulk by purposely creating in the crystal lattice of the semiconductor hydrocarbon bonds with the semiconductor, typically Si or Ge, constituting effective organic group substituents of semiconductor atoms in the crystalline domains. An important enhancement of the factor of merit Z of such a modified electrically conductive doped semiconductor is obtained without resorting to nanometric cross sectional dimensions in order to rely on surface scattering eventually enhanced by making the surface highly irregular and/or creating nanocavities within the bulk of the conductive material. A determinant scattering of phonons migrating under the influence and in the direction of a temperature gradient in the homogeneous semiconductor takes place at the organic groups substituents in the crystalline doped semiconductor bulk. Fabrication processes and Seebeck-Peltier energy conversion devices are exemplarily described. | 03-26-2015 |