Patent application number | Description | Published |
20110088188 | HAIR BRUSH - A hair brush is disclosed herein that includes a handle, a base and a plurality of bristles, wherein the base and the plurality of bristles are one single continuous component. A method of producing a sanitary hair brush comprises: a) providing at least one curable material, b) injection molding the at least one material into a mold in order to produce a base, a handle, a plurality of bristles or a combination thereof as one single continuous component. | 04-21-2011 |
20140246039 | HAIR BRUSH AND OTHER BRISTLED ITEMS, AND THEIR METHODS OF MANUFACTURE AND USE - A hair brush is disclosed herein that includes a handle, a base and a plurality of bristles, wherein the base and the plurality of bristles are one single continuous component. A method of producing a sanitary hair brush comprises: a) providing at least one curable material, b) injection molding the at least one material into a mold in order to produce a base, a handle, a plurality of bristles or a combination thereof as one single continuous component. Another method of producing a sanitary bristled item includes: a) providing at least two curable materials, wherein a first curable material is chemically different from a second curable material, b) injection molding the at least two materials separately into a mold in order to produce a base, a handle, a plurality of bristles or a combination thereof as one single continuous component, wherein the first curable material is used to form the plurality of bristles and the second curable material is used to form the handle and the base. Bristled items produced from these methods are also contemplated. | 09-04-2014 |
Patent application number | Description | Published |
20080290374 | LAYOUT FOR HIGH DENSITY CONDUCTIVE INTERCONNECTS - In one embodiment of the present invention, a method for connecting a plurality of bit lines to sense circuitry comprises providing a plurality of bit lines extending from a memory array in a first metal layer. The plurality of bit lines are separated from each other by an average spacing x in a first region of the first metal layer. The method further comprises elevating a portion of the plurality of bit lines into a second metal layer overlying the first metal layer. The elevated bit lines are separated from each other by an average spacing y in the second metal layer, with y>x. The method further comprises extending a portion of the plurality of bit lines into a second region of the first metal layer. The extended bit lines are separated from each other by an average spacing z in the second region of the first metal layer, with z>x. The method further comprises connecting a bit line in the second metal layer and a bit line in the first metal layer to the sense circuitry. | 11-27-2008 |
20090102522 | POWER ON RESET CIRCUITRY - One or more embodiments of the present disclosure provide methods, devices, and systems for operating power on reset (POR) circuitry. One method embodiment includes providing a voltage to a POR circuit of the system, detecting when the voltage reaches a number of different trip levels, maintaining a count of the number of times an output signal of the POR circuit trips in response to a detected reaching of one of the number of different trip levels, and adjusting the trip level to be detected based at least partially on the count. | 04-23-2009 |
20090116283 | Controlling a memory device responsive to degradation - Embodiments of the present invention disclosed herein include devices, systems and methods, such as those directed to non-volatile memory devices and systems capable of determining a degradation parameter associated with one or more memory cells. Disclosed devices and systems according to embodiments of the present invention include those that utilize the degradation parameter to adjust control signals coupled to the memory cells. | 05-07-2009 |
20100202217 | NAND FLASH MEMORY PROGRAMMING - A method of charging a floating gate in a nonvolatile memory cell comprises bringing a substrate channel within the memory cell to a first voltage, bringing a control gate to a programming voltage, and floating the substrate channel voltage while the control gate is at the programming voltage. Memory devices include state machines or controllers operable to perform the described method, and operation of such a state machine, memory device, and information handling system are described. | 08-12-2010 |
20100315874 | USE OF EMERGING NON-VOLATILE MEMORY ELEMENTS WITH FLASH MEMORY - Memory devices and methods of operating memory devices are provided, such as those that involve a memory architecture that replaces typical static and/or dynamic components with emerging non-volatile memory (NV) elements. The emerging NV memory elements can replace conventional latches, can serve as a high speed interface between a flash memory array and external devices and can also be used as high performance cache memory for a flash memory array. | 12-16-2010 |
20110006347 | LAYOUT FOR HIGH DENSITY CONDUCTIVE INTERCONNECTS - In one embodiment of the present invention, a method for connecting a plurality of bit lines to sense circuitry comprises providing a plurality of bit lines extending from a memory array in a first metal layer. The plurality of bit lines are separated from each other by an average spacing x in a first region of the first metal layer. The method further comprises elevating a portion of the plurality of bit lines into a second metal layer overlying the first metal layer. The elevated bit lines are separated from each other by an average spacing y in the second metal layer, with y>x. The method further comprises extending a portion of the plurality of bit lines into a second region of the first metal layer. The extended bit lines are separated from each other by an average spacing z in the second region of the first metal layer, with z>x. The method further comprises connecting a bit line in the second metal layer and a bit line in the first metal layer to the sense circuitry. | 01-13-2011 |
20110063923 | TRENCH MEMORY STRUCTURE OPERATION - Memory cells utilizing dielectric charge carrier trapping sites formed in trenches provide for non-volatile storage of data. The memory cells of the various embodiments have two control gates. One control gate is formed adjacent the trench containing the charge carrier trap. The other control gate has a portion formed over the trench, and, for certain embodiments, this control gate may extend into the trench. The charge carrier trapping sites may be discrete formations on a sidewall of a trench, a continuous layer extending from one sidewall to the other, or plugs extending between sidewalls. | 03-17-2011 |
20110122699 | CONTROLLING A MEMORY DEVICE RESPONSIVE TO DEGRADATION - Embodiments of the present invention disclosed herein include devices, systems and methods, such as those directed to non-volatile memory devices and systems capable of determining a degradation parameter associated with one or more memory cells. Disclosed devices and systems according to embodiments of the present invention include those that utilize the degradation parameter to adjust control signals coupled to the memory cells. | 05-26-2011 |
20110141813 | USE OF EMERGING NON-VOLATILE MEMORY ELEMENTS WITH FLASH MEMORY - Memory devices and methods of operating memory devices are provided, such as those that involve a memory architecture that replaces typical static and/or dynamic components with emerging non-volatile memory (NV) elements. The emerging NV memory elements can replace conventional latches, can serve as a high speed interface between a flash memory array and external devices and can also be used as high performance cache memory for a flash memory array. | 06-16-2011 |
20110280079 | NAND FLASH MEMORY PROGRAMMING - A method of charging a floating gate in a nonvolatile memory cell comprises bringing a substrate channel within the memory cell to a first voltage, bringing a control gate to a programming voltage, and floating the substrate channel voltage while the control gate is at the programming voltage. Memory devices include state machines or controllers operable to perform the described method, and operation of such a state machine, memory device, and information handling system are described. | 11-17-2011 |
20130003460 | USE OF EMERGING NON-VOLATILE MEMORY ELEMENTS WITH FLASH MEMORY - Memory devices and methods of operating memory devices are provided, such as those that involve a memory architecture that replaces typical static and/or dynamic components with emerging non-volatile memory (NV) elements. The emerging NV memory elements can replace conventional latches, can serve as a high speed interface between a flash memory array and external devices and can also be used as high performance cache memory for a flash memory array. | 01-03-2013 |
20130033939 | FUNCTIONAL DATA PROGRAMMING AND READING IN A MEMORY - Methods for functional programming memory cells and apparatuses are disclosed. One such method for functional programming includes encoding a group of data with a function to generate representative data and programming the representative data to the memory. In one embodiment, the representative data is a pattern of threshold voltages to be programmed to a group of memory cells. | 02-07-2013 |
20130242657 | USE OF EMERGING NON-VOLATILE MEMORY ELEMENTS WITH FLASH MEMORY - Memory devices and methods of operating memory devices are provided, such as those that involve a memory architecture that replaces typical static and/or dynamic components with emerging non-volatile memory (NV) elements. The emerging NV memory elements can replace conventional latches, can serve as a high speed interface between a flash memory array and external devices and can also be used as high performance cache memory for a flash memory array. | 09-19-2013 |
Patent application number | Description | Published |
20140022847 | NAND FLASH MEMORY PROGRAMMING - A method of charging a floating gate in a nonvolatile memory cell comprises bringing a substrate channel within the memory cell to a first voltage, bringing a control gate to a programming voltage, and floating the substrate channel voltage while the control gate is at the programming voltage. Memory devices include state machines or controllers operable to perform the described method, and operation of such a state machine, memory device, and information handling system are described. | 01-23-2014 |
20140063947 | ERASABLE BLOCK SEGMENTATION FOR MEMORY - Various embodiments comprise apparatuses such as those having a block of memory divided into sub-blocks that share a common data line. Each of the sub-blocks of the block of memory corresponds to a respective one of a number of segmented sources. Each of the segmented sources is electrically isolated from the other segmented sources of the block of memory. Additional apparatuses and methods of operation are described. | 03-06-2014 |
20140115373 | APPARATUSES AND METHODS AND FOR PROVIDING POWER RESPONSIVE TO A POWER LOSS - Apparatuses and methods for providing power responsive a power loss are disclosed herein. A power chip may comprise a power sensor, a write command control logic, and an array. The power sensor may be configured to detect a power loss of a power supply and provide a power loss control signal responsive, at least in part, to detecting the power loss of the power supply. The write command control logic may be coupled to the power sensor and may be configured to receive the power loss control signal. The write command control logic may be further configured to provide a write command responsive, at least in part, to receipt of the power loss control signal. The array may include a plurality of capacitors configured to store power and further configured to provide power during the power loss. | 04-24-2014 |
20150063024 | MEMORY DEVICES WITH LOCAL AND GLOBAL DEVICES AT SUBSTANTIALLY THE SAME LEVEL ABOVE STACKED TIERS OF MEMORY CELLS AND METHODS - In an embodiment, a memory device includes a stack of tiers of memory cells, a tier of local devices at a level above the stack of tiers of memory cells, and a tier of global devices at substantially a same level as the tier of local devices. A local device may provide selective access to a data line. A global device may provide selective access to a global access line. A tier of memory cells may be selectively coupled to a global access line by the global device of the tier of global devices. | 03-05-2015 |