Patent application number | Description | Published |
20090119089 | METHOD, APPARATUS AND FULL-SYSTEM SIMULATOR FOR SPEEDING MMU SIMULATION - A method, apparatus, and full-system simulator for speeding memory management unit simulation with direct address mapping on a host system, the host system supporting a full-system simulator, on which a guest system is simulated, the method comprising the following steps: setting a border in the logical space assigned for the full-system simulator by the host system, thereby dividing the logical space into a safe region and a simulator occupying region; shifting the full-system simulator itself from the occupied original host logical space to the simulator occupying region; and reserving the safe region for use with at least part of the guest system. | 05-07-2009 |
20110258421 | Architecture Support for Debugging Multithreaded Code - Mechanisms are provided for debugging application code using a content addressable memory. The mechanisms receive an instruction in a hardware unit of a processor of the data processing system, the instruction having a target memory address that the instruction is attempting to access. A content addressable memory (CAM) associated with the hardware unit is searched for an entry in the CAM corresponding to the target memory address. In response to an entry in the CAM corresponding to the target memory address being found, a determination is made as to whether information in the entry identifies the instruction as an instruction of interest. In response to the entry identifying the instruction as an instruction of interest, an exception is generated and sent to one of an exception handler or a debugger application. In this way, debugging of multithreaded applications may be performed in an efficient manner. | 10-20-2011 |
20110265068 | Single Thread Performance in an In-Order Multi-Threaded Processor - A mechanism is provided for improving single-thread performance for a multi-threaded, in-order processor core. In a first phase, a compiler analyzes application code to identify instructions that can be executed in parallel with focus on instruction-level parallelism and removing any register interference between the threads. The compiler inserts as appropriate synchronization instructions supported by the apparatus to ensure that the resulting execution of the threads is equivalent to the execution of the application code in a single thread. In a second phase, an operating system schedules the threads produced in the first phase on the hardware threads of a single processor core such that they execute simultaneously. In a third phase, the microprocessor core executes the threads specified by the second phase such that there is one hardware thread executing an application thread. | 10-27-2011 |
20110296138 | FAST REMOTE COMMUNICATION AND COMPUTATION BETWEEN PROCESSORS - A method, system, and computer usable program product for fast remote communication and computation between processors are provided in the illustrative embodiments. A direct core to core communication unit (DCC) is configured to operate with a first processor, the first processor being a remote processor. A memory associated with the DCC receives a set of bytes, the set of bytes being sent from a second processor. An operation specified in the set of bytes is executed at the remote processor such that the operation is invoked without causing a software thread to execute. | 12-01-2011 |
20120144395 | Inter-Thread Data Communications In A Computer Processor - Inter-thread data communications in a computer processor with multiple hardware threads of execution, each hardware thread operatively coupled for communications through an inter-thread communications controller, where inter-thread communications is carried out by the inter-thread communications controller and includes: registering, responsive to one or more RECEIVE opcodes, one or more receiving threads executing the RECEIVE opcodes; receiving, from a SEND opcode of a sending thread, specifications of a number of derived messages to be sent to receiving threads and a base value; generating the derived messages, incrementing the base value once for each registered receiving thread so that each derived message includes a single integer as a separate increment of the base value; sending, to each registered receiving thread, a derived message; and returning, to the sending thread, an actual number of derived messages received by receiving threads. | 06-07-2012 |
20120144396 | Creating A Thread Of Execution In A Computer Processor - Creating a thread of execution in a computer processor, including copying, by a hardware processor opcode called by a user-level process, with no operating system involvement, register contents from a parent hardware thread to a child hardware thread, the child hardware thread being in a wait state, and changing, by the hardware processor opcode, the child hardware thread from the wait state to an ephemeral run state. | 06-07-2012 |
20120173928 | Analyzing Simulated Operation Of A Computer - Analyzing simulated operation of a computer including loading user-defined dynamically linked analysis libraries that each include specifications of events to be traced for analysis, including: executing, in separate hardware threads, one trace buffer handler for each analysis library, and associating, with each trace buffer handler, one or more analysis functions; translating static binary instructions for the simulated computer into binary instructions for the executing computer, including: inserting, into the translation, implementing code for each specification of an event to be traced and inserting, into the translation for each static instruction, a memory address of a separate static instruction buffer; executing the translation, including executing the implementing code and generating, in a trace buffer, one or more trace records for each specified event; and processing the trace buffer, including calling analysis functions and associating by the analysis functions through the separate static instruction buffers event analysis data with static instructions. | 07-05-2012 |
20120191946 | FAST REMOTE COMMUNICATION AND COMPUTATION BETWEEN PROCESSORS - A method for fast remote communication and computation between processors is provided in the illustrative embodiments. A direct core to core communication unit (DCC) is configured to operate with a first processor, the first processor being a remote processor. A memory associated with the DCC receives a set of bytes, the set of bytes being sent from a second processor. An operation specified in the set of bytes is executed at the remote processor such that the operation is invoked without causing a software thread to execute. | 07-26-2012 |
20120203979 | Architecture Support for Debugging Multithreaded Code - Mechanisms are provided for debugging application code using a content addressable memory. The mechanisms receive an instruction in a hardware unit of a processor of the data processing system, the instruction having a target memory address that the instruction is attempting to access. A content addressable memory (CAM) associated with the hardware unit is searched for an entry in the CAM corresponding to the target memory address. In response to an entry in the CAM corresponding to the target memory address being found, a determination is made as to whether information in the entry identifies the instruction as an instruction of interest. In response to the entry identifying the instruction as an instruction of interest, an exception is generated and sent to one of an exception handler or a debugger application. In this way, debugging of multithreaded applications may be performed in an efficient manner. | 08-09-2012 |
20120216204 | CREATING A THREAD OF EXECUTION IN A COMPUTER PROCESSOR - Creating a thread of execution in a computer processor, including copying, by a hardware processor opcode called by a user-level process, with no operating system involvement, register contents from a parent hardware thread to a child hardware thread, the child hardware thread being in a wait state, and changing, by the hardware processor opcode, the child hardware thread from the wait state to an ephemeral run state. | 08-23-2012 |
20120317228 | MANAGING DATA ACCESS IN MOBILE DEVICES - A method for managing data access in a mobile device is provided in the illustrative embodiments. Using a data manager executing in the mobile device, a data item is configured in a data model. A value parameter of the data item is populated with data and a status parameter of the data item is populated with a status indication. A subscription to the data item is received from a mobile application executing in the mobile device. In response to the subscription, the data and the status of the data item are sent to the mobile application. | 12-13-2012 |
20120317234 | MANAGING DATA ACCESS IN MOBILE DEVICES - A, system, and computer program product for managing data access in a mobile device are provided in the illustrative embodiments. Using a data manager executing in the mobile device, a data item is configured in a data model. A value parameter of the data item is populated with data and a status parameter of the data item is populated with a status indication. A subscription to the data item is received from a mobile application executing in the mobile device. In response to the subscription, the data and the status of the data item are sent to the mobile application. | 12-13-2012 |
20130159990 | UPDATING FIRMWARE USING A MOBILE COMMUNICATION DEVICE - A method, system, and computer program product for updating firmware using a mobile communication device are provided in the illustrative embodiments. At the mobile communication device from a data processing system that includes the firmware, a current version information of the firmware is received. At the mobile communication device, an update of the firmware is stored on a data storage associated with the mobile communication device. From the mobile communication device, the data processing system is instructed to reboot using the update stored on the data storage associated with the mobile communication device. | 06-20-2013 |
20140013073 | USING LARGE FRAME PAGES WITH VARIABLE GRANULARITY - The page tables in existing art are modified to allow virtual address resolution by mapping to multiple overlapping entries, and resolving a physical address from the most specific entry. This enables more efficient use of system resources by allowing smaller frames to shadow larger frames. A page table is selected. When a virtual address in a request corresponds to an entry in the page table, which identifies a next page table associated with the large frame, a determination is made that the virtual address corresponds to an entry in the next page table, the entry in the next page table referencing a small frame overlay for the large frame. The virtual address is mapped to a physical address in the small frame overlay using data of the entry in the next page table. The physical address in a process-specific view of the large frame is returned. | 01-09-2014 |
20140040577 | Automatic Use of Large Pages - A mechanism is provided for automatic use of large pages. An operating system loader performs aggressive contiguous allocation followed by demand paging of small pages into a best-effort contiguous and naturally aligned physical address range sized for a large page. The operating system detects when the large page is fully populated and switches the mapping to use large pages. If the operating system runs low on memory, the operating system can free portions and degrade gracefully. | 02-06-2014 |
20140040901 | INTER-THREAD DATA COMMUNICATIONS IN A COMPUTER PROCESSOR - A first set of one or more hardware threads for receiving messages sent from hardware threads are registered. After receiving indications of a message location value and a number, the message location value is increments and sent to a different hardware thread of the first set of one or more hardware threads until the message location value has been incremented the number of times or a criterion for interrupting the incrementing and sending is satisfied. An actual number of times the message location value was incremented is indicated to a hardware thread that sent the indications of the message location value and the number. | 02-06-2014 |
20140163945 | MEMORY FRAME PROXY ARCHITECTURE FOR SYNCHRONIZATION AND CHECK HANDLING IN A SIMULATOR - A simulation technique that handles accesses to a frame of memory via a proxy object provides improved throughput in simulation environments. The proxy object, if present, processes the access at a head of a linked list of frames. If a check frame is not inserted in the list, the memory frame handles the request directly, but if a check frame is inserted, then the check operation is performed. The check frame can be a synchronization frame that blocks access to a memory frame while the check frame is present, or the check frame may be a breakpoint, watch or exception frame that calls a suitable handling routine. Additional check frames may be chained between the interface and the memory subsystem to handle synchronization, breakpoints, memory watches or other accesses to or information gathering associated with the memory frame. | 06-12-2014 |
20140163946 | MEMORY FRAME ARCHITECTURE FOR INSTRUCTION FETCHES IN SIMULATION - A simulation technique that handles accesses to a frame of instruction memory by inserting a command object between a frame proxy and a memory frame provides improved throughput in simulation environments. The instruction frame, if present, processes the access to the frame. If an instruction frame is not present for the accessed frame, the memory frame handles the request directly. The instruction frame caches fetched and decoded instructions and may be inserted at the first access to a corresponding instruction memory frame. The instruction frame can track write accesses to instruction memory so that changes to the instruction memory can be reflected in the state of the instruction frame. Additional check frames may be chained between the interface and the memory frame to handle breakpoints, instruction memory watches or other access checks on the instruction memory frame. | 06-12-2014 |
20140163947 | MEMORY FRAME ARCHITECTURE FOR INSTRUCTION FETCHES IN SIMULATION - A simulation technique that handles accesses to a frame of instruction memory by inserting a command object between a frame proxy and a memory frame provides improved throughput in simulation environments. The instruction frame, if present, processes the access to the frame. If an instruction frame is not present for the accessed frame, the memory frame handles the request directly. The instruction frame caches fetched and decoded instructions and may be inserted at the first access to a corresponding instruction memory frame. The instruction frame can track write accesses to instruction memory so that changes to the instruction memory can be reflected in the state of the instruction frame. Additional check frames may be chained between the interface and the memory frame to handle breakpoints, instruction memory watches or other access checks on the instruction memory frame. | 06-12-2014 |
20150082324 | Efficient Interrupt Handling - A mechanism is provided for handling interrupt actions for inter-thread communication. In association with a first processor thread, a thread action data structure is provided that comprises a non-blocking synchronization data structure and an internal list data structure of pending interrupts having no form of synchronization. A post of an interrupt action is received from a second processor thread to the thread action data structure associated with the first processor thread, where the interrupt action is added to the non-blocking synchronization data structure of the thread action data structure. The interrupt action is moved from the non-blocking synchronization data structure to the internal list data structure of pending interrupts for handling by the first processor thread. The internal list data structure of pending interrupts is processed to thereby handle interrupt actions moved to the internal list data structure. | 03-19-2015 |