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Geva
Guillermo Geva, Montrouge FR
| Patent application number | Description | Published |
|---|---|---|
| 20090065917 | Multi-Standards Compliant Card Body - A card body comprises a module-receiving part ( | 03-12-2009 |
Robert Geva, Cupertino, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100042765 | Dynamically Migrating Channels - In one embodiment, the present invention includes a method of determining a relative priority between a first agent and a second agent, and assigning the first agent to a first channel and the second agent to a second channel according to the relative priority. Depending on the currently programmed status of the channels, information stored in at least one of the channels may be dynamically migrated to another channel based on the assignments. Other embodiments are described and claimed. | 02-18-2010 |
| 20100122073 | HANDLING EXCEPTIONS IN SOFTWARE TRANSACTIONAL MEMORY SYSTEMS - A method and apparatus for handling exceptions during execution of a transaction is herein described. A compiler associates a transaction exception handler (TEH) with a transaction in program code, such as through insertion of a call to the TEH. The TEH is also associated with an exception data structure, such as an unwind table, that is utilized during runtime to call an appropriate handler in response to an exception. Additionally, the TEH code is generated by the compiler and inserted into the program code. Upon encountering an exception during execution of the transaction, the TEH is capable of dynamically resizing the transaction to the point of the exception through an attempted commit. | 05-13-2010 |
Robert Y. Geva, Cupertino, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100332768 | FLEXIBLE READ- AND WRITE-MONITORED AND BUFFERED MEMORY BLOCKS - A computing system includes a number of threads. The computing system is configured to allow for monitoring and testing memory blocks in a cache memory to determine effects on memory blocks by various agents. The system includes a processor. The processor includes a mechanism implementing an instruction set architecture including instructions accessible by software. The instructions are configured to: set per-hardware-thread, for a first thread, memory access monitoring indicators for a plurality of memory blocks, and test whether any monitoring indicator has been reset by the action of a conflicting memory access by another agent. The processor further includes mechanism configured to: detect conflicting memory accesses by other agents to the monitored memory blocks, and upon such detection of a conflicting access, reset access monitoring indicators corresponding to memory blocks having conflicting memory accesses, and remember that at least one monitoring indicator has been so reset. | 12-30-2010 |
| 20100332807 | PERFORMING ESCAPE ACTIONS IN TRANSACTIONS - Performing non-transactional escape actions within a hardware based transactional memory system. A method includes at a hardware thread on a processor beginning a hardware based transaction for the thread. Without committing or aborting the transaction, the method further includes suspending the hardware based transaction and performing one or more operations for the thread, non-transactionally and not affected by: transaction monitoring and buffering for the transaction, an abort for the transaction, or a commit for the transaction. After performing one or more operations for the thread, non-transactionally, the method further includes resuming the transaction and performing additional operations transactionally. After performing the additional operations, the method further includes either committing or aborting the transaction. | 12-30-2010 |
| 20100332808 | MINIMIZING CODE DUPLICATION IN AN UNBOUNDED TRANSACTIONAL MEMORY SYSTEM - Minimizing code duplication in an unbounded transactional memory system. A computing apparatus including one or more processors in which it is possible to use a set of common mode-agnostic TM barrier sequences that runs on legacy ISA and extended ISA processors, and that employs hardware filter indicators (when available) to filter redundant applications of TM barriers, and that enables a compiled binary representation of the subject code to run correctly in any of the currently implemented set of transactional memory execution modes, including running the code outside of a transaction, and that enables the same compiled binary to continue to work with future TM implementations which may introduce as yet unknown future TM execution modes. | 12-30-2010 |
Yacov Geva, Chicago, IL US
| Patent application number | Description | Published |
|---|---|---|
| 20100249541 | Methods and Apparatus for Processing Physiological Data Acquired from an Ambulatory Physiological Monitoring Unit - A physiologic monitoring system and corresponding methods provide rapid and detailed analysis of data for one or more physiologic parameters to achieve a quick and accurate medical diagnosis. An ambulatory physiological monitoring unit acquires physiologic data, automatically analyzes it to detect an event, and transmits information regarding the event and physiologic data associated with the event across a communications network to a monitoring center, where the event information is analyzed and triaged. The monitoring center can also perform a retrospective analysis based on the physiological data associated with the event to provide an in-depth analysis of the detected event and an accurate diagnosis. The monitoring center can also request additional or different physiological data to refine the analysis. As a result, the physiological monitoring system and corresponding methods can ensure that timely and appropriate intervention is taken to reduce a patient's discomfort, pain, injury, or risk of death. | 09-30-2010 |