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Gerhard, MN
Adrian C. Gerhard, Rochester, MN US
| Patent application number | Description | Published |
|---|---|---|
| 20100199039 | Systems and Methods for Optimizing Host Reads and Cache Destages in a Raid System - In one aspect, a method of a storage adapter controlling a redundant array of independent disks (RAID) may be provided. The method may include examining performance curves of a storage adapter with a write cache, determining if an amount of data entering the write cache of the storage adapter has exceeded a threshold, and implementing a strategy based on the determining operation. The strategy may include one of coupling Read-XOR/Write operations and providing priority reordering of Read operations over the Read-XOR/Write operations in order to minimize host read response time if data entering the write cache is less than the threshold, and allowing all Read operations and Read-XOR/Write operations to be queued at the device using simple tags in order to achieve maximum throughput if data entering the write cache is greater than the threshold. Additional aspects are described. | 08-05-2010 |
| 20100262868 | Managing Possibly Logically Bad Blocks in Storage Devices - If data is lost a possibly logically bad pattern is placed in a standard size data block in a storage device, and the Logical Block Address associated with the data block is inserted in a Bad Block Table. The possibly logically bad pattern is able to be detected, and the Bad Block Table is checked to determine if the data block to be read is in fact Logically Bad. A data check response may be given to a host if a Logical Block Address associated with the standard size data block is present in a Bad Block Table. The possibly logically bad pattern may have a first predefined data portion and a second predefined data portion and may be repeated the requisite number of instances to fill the standard size data block. | 10-14-2010 |
Adrian Cuenin Gerhard, Rochester, MN US
| Patent application number | Description | Published |
|---|---|---|
| 20080201608 | RECOVERING FROM ABNORMAL INTERRUPTION OF A PARITY UPDATE OPERATION IN A DISK ARRAY SYSTEM - Data associated with the state of a parity update operation in a disk array system such as a RAID-6 system is stored during performance of the operation so that, in the event the operation is interrupted, recovery may be initiated using the stored data. The stored data may include a state indicator that is indicative of the status of the parity update operation, and snapshot data (e.g., a delta value indicative of a difference between new and old data) captured during the parity update operation. | 08-21-2008 |
| 20080229148 | ENHANCED ERROR IDENTIFICATION WITH DISK ARRAY PARITY CHECKING - When parity checking in a disk array such as a RAID-6 system determines data and parity information is unsynchronized, additional calculations are performed to determine whether the error may be attributed to faulty data on a disk drive or to a more systemic problem such as a faulty controller. In particular, for each particular error detected, the parity generating information is analyzed to determine if each error involves a common disk index. If so, the data can be corrected on that disk; if not other corrective procedures are implemented. | 09-18-2008 |
| 20080229155 | ENHANCED ERROR IDENTIFICATION WITH DISK ARRAY PARITY CHECKING - When parity checking in a disk array such as a RAID-6 system determines data and parity information is unsynchronized, additional calculations are performed to determine whether the error may be attributed to faulty data on a disk drive or to a more systemic problem such as a faulty controller. In particular, for each particular error detected, the parity generating information is analyzed to determine if each error involves a common disk index. If so, the data can be corrected on that disk; if not other corrective procedures are implemented. | 09-18-2008 |
Elizabeth L. Gerhard, Rochester, MN US
| Patent application number | Description | Published |
|---|---|---|
| 20090116324 | Apparatus for Guaranteed Write Through in Domino Read SRAM'S - In a digital device for facilitating recovery of a precharged dot line, periodically precharged by a precharge signal, that has been prematurely discharged as a result of an early read condition, a data input signal can have a selected one of a first value and a second value. The first value is a value that would be reflected by the dot line being in a charged state. A logic device that is responsive to the data input signal causes charge to be applied to the dot line when the data signal has the first value. | 05-07-2009 |
| 20090175107 | Apparatus for and Method of Current Leakage Reduction in Static Random Access Memory Arrays - A novel and useful mechanism for reducing current leakage in a static random access memory array which significantly reduces the power requirements of the memory array. The method enables the steady state of all local and global bit lines in an SRAM array to be discharged during both active and inactive modes. The memory array consists of memory cells having an N channel field effect transistor read stack. A mechanism is provided to evaluate data from memory cells where the steady state of local and global read bit lines is discharged. | 07-09-2009 |
| 20100195408 | Non-Body Contacted Sense Amplifier with Negligible History Effect - In a method of mitigating hysteresis effect in a sense amplifier circuit, a data value is sensed from a data source with the sense amplifier during a first period. The data value is stored in a latch. The data valued stored in the latch is inverted, thereby generating an inverted data value. The data source is isolated from the sense amplifier and the inverted data value is read with the sense amplifier during a second period immediately following the first period. | 08-05-2010 |
Elizabeth Lair Gerhard, Rochester, MN US
| Patent application number | Description | Published |
|---|---|---|
| 20080273402 | APPARATUS FOR IMPLEMENTING DOMINO SRAM LEAKAGE CURRENT REDUCTION - A method and apparatus implementing domino static random access memory (SRAM) leakage current reduction include a local evaluation circuit coupled to true and complement bit lines of a pair of local SRAM cell groups, receives precharge signals and provides an output connected to a global dot line. A sleep input is applied to SRAM sleep logic and a write driver including sleep control. Data true and data complement outputs of the write driver are forced to a respective selected level to discharge the bit lines and global dot lines when the sleep input transitions high. Discharging the bit lines and global dot lines is implemented through gating in the write driver without requiring any additional devices in the local evaluation circuit. | 11-06-2008 |
| 20090285039 | METHOD AND APPARATUS FOR LOCALLY GENERATING A VIRTUAL GROUND FOR WRITE ASSIST ON COLUMN SELECTED SRAM CELLS - A method and apparatus for write assist for a static random access memory (SRAM) array, is provided, which increases the write ability of the SRAM cell by locally raising the source voltage. One embodiment involves locally generating a virtual ground for write assist on column selected SRAM cells, including locally raising the source voltage to increase the write ability of the SRAM cell; wherein locally raising the source voltage comprises locally generating a virtual source/ground node for boosting the write ability of a column of SRAM cells without using an additional on-chip or off-chip supply; thereby decreasing the voltage differential across the source and supply of the column of SRAM cells during a write, and restoring the standard chip differential during a read. | 11-19-2009 |
| 20090287971 | METHOD AND APPARATUS FOR TESTING A RANDOM ACCESS MEMORY DEVICE - A method and apparatus for testing a random access memory device is provided. One embodiment involves providing an interface between Logic Built in Self Test (LBIST) and Array Built in Self Test (ABIST) paths for memory testing, including providing a cross-coupled NAND device with an LBIST test path; configuring the cross-coupled NAND device for interfacing ABIST and LBIST paths by modeling a worst case scenario for timing from a domino read static random access memory (SRAM) array; and modifying data in the cross-coupled NAND device using an LBIST controlled data path at essentially the latest point in time when a read may propagate from the array to provide full AC test coverage of down stream logic. | 11-19-2009 |