Patent application number | Description | Published |
20090110898 | HIGH RESISTIVITY SOI BASE WAFER USING THERMALLY ANNEALED SUBSTRATE - A method of forming a semiconductor-on-insulator (SOI) substrate using a thermal annealing process to provide a semiconductor base wafer having a thin high resistivity surface layer that is positioned at the interface with the buried insulating layer is provided. Specifically, the inventive method fabricates an a semiconductor-on-insulator (SOI) substrate having an SOI layer and a semiconductor base wafer that are separated, at least in part, by a buried insulating layer, wherein the semiconductor base wafer includes a high resistivity (HR) surface layer located on a lower resistivity semiconductor portion of the semiconductor base wafer, and the HR surface layer forms an interface with the buried insulating layer. | 04-30-2009 |
20100132760 | BACKSIDE CONTACTING ON THIN LAYER PHOTOVOLTAIC CELLS - A method of backside contacting of thin layer photovoltaic cells having Si elements as well as thin film cells, like CIGS, is provided, including the following steps:
| 06-03-2010 |
20100233386 | PRECISION SEPARATION OF PV THIN FILM STACKS - A method for manufacturing thin film panels comprises providing a laser patterning system, depositing a base layer on a glass substrate, separating the base layer by scribing a plurality of separation lines corresponding with a predefined scribe pattern, depositing a functional layer on the base layer, determining a first base layer separation edge, moving the translation stage by a first distance, activating the laser array and moving the translation stage by a second distance, deactivating the laser array, determining subsequent separation edges of the base layer and scribing lines therein, depositing a top layer on the functional layer, determining a first functional layer separation edge, operating the stepper motor to move the translation stage by a third distance, activating the laser array and moving the translation stage by a fourth distance, deactivating the laser array, and determining subsequent separation edges of the functional layer and scribing lines therein. | 09-16-2010 |
20110120519 | Method of Manufacturing a Photovoltaic Cell - A method of manufacturing a photovoltaic cell using a semiconductor wafer having a front side and a rear side, wherein the photovoltaic cell produces electricity when the front side of the semiconductor wafer is illuminated., the method comprising the steps of: | 05-26-2011 |
20110204524 | STRUCTURES AND METHODS OF FORMING PRE FABRICATED DEEP TRENCH CAPACITORS FOR SOI SUBSTRATES - Structures and methods are provided for forming pre-fabricated deep trench capacitors for SOI substrates. The method includes forming a trench in a substrate and forming a dielectric material in the trench. The method further includes depositing a conductive material over the dielectric material in the trench and forming an insulator layer over the conductive material and the substrate. | 08-25-2011 |
20130196493 | SILICON-ON-INSULATOR SUBSTRATE AND METHOD OF FORMING - Silicon-on-insulator (SOI) structures and related methods of forming such structures. In one case, a method includes providing a silicon-on-insulator (SOI) handle substrate having: a substantially uniform resistivity profile along a depth of the handle substrate; and an interstitial oxygen (O | 08-01-2013 |
20130244348 | FINE TUNING HIGHLY RESISTIVE SUBSTRATE RESISTIVITY AND STRUCTURES THEREOF - Methods are provided for fine tuning substrate resistivity. The method includes measuring a resistivity of a substrate after an annealing process, and fine tuning a subsequent annealing process to achieve a target resistivity of the substrate. The fine tuning is based on the measured resistivity. | 09-19-2013 |
20140202529 | SILICON SOLAR CELL MANUFACTURE - A silicon solar cell is manufactured by providing a carrier plate, and by applying a first contact pattern to the carrier plate. The first contact pattern includes a set of first laminar contacts. The silicon solar cell is further manufactured by applying a multitude of silicon slices to the first contact pattern, and by applying a second contact pattern to the multitude of silicon slices. Each first laminar contact of the set of first laminar contacts is in spatial laminar contact with maximally two silicon slices. The second contact pattern includes a set of second laminar contacts. Each second laminar contact of the set of second laminar contacts is in spatial laminar contact with maximally two silicon slices. | 07-24-2014 |
20140264756 | STACKED INTEGRATED CIRCUIT - The formation of TSVs (through substrate vias) for 3D applications has proven to be defect dependent upon the type of starting semiconductor substrate employed. In addition to the initial formation of TSVs via Bosch processing, backside 3D wafer processing has also shown a defect dependency on substrate type. High yield of TSV formation can be achieved by utilizing a substrate that embodies bulk micro defects (BMD) at a density between 1e4/cc (particles per cubic centimeter) and 1e7/cc and having equivalent diameter less than 55 nm (nanometers). | 09-18-2014 |
20150072504 | HIGH LINEARITY SOI WAFER FOR LOW-DISTORTION CIRCUIT APPLICATIONS - According to a method herein, a first side of a substrate is implanted with a first material to change a crystalline structure of the first side of the substrate from a first crystalline state to a second crystalline state, after the first material is implanted. A second material is deposited on the first side of the substrate, after the first material is implanted. A first side of an insulator layer is bonded to the second material on the first side of the substrate. Integrated circuit devices are formed on a second side of the insulator layer, opposite the first side of the insulator layer, after the insulator layer is bonded to the second material. The integrated circuit devices are thermally annealed. The first material maintains the second crystalline state of the first side of the substrate during the annealing. | 03-12-2015 |