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Gerben Doornbos
Gerben Doornbos, Kessel-Lo BE
| Patent application number | Description | Published |
|---|---|---|
| 20100028809 | DOUBLE PATTERNING FOR LITHOGRAPHY TO INCREASE FEATURE SPATIAL DENSITY - A method of forming a pattern in at least one device layer in or on a substrate comprises: coating the device layer with a first photoresist layer; exposing the first photoresist using a first mask; developing the first photoresist layer to form a first pattern on the substrate; coating the substrate with a protection layer; treating the protection layer to cause a change therein where it is in contact with the first photoresist, to render the changed protection layer substantially immune to a subsequent exposure and/or developing step; coating the substrate with a second photoresist layer; exposing the second photoresist layer using a second mask; and developing the second photoresist layer to form a second pattern on the substrate without significantly affecting the first pattern in the first photoresist layer, wherein the first and second patterns together define interspersed features having a spartial frequency greater than that of the features defined in each of the first and second patterns separately. The process has particular utility in defining source, drain and fin features of finFET devices with a smaller feature size than otherwise achievable with the prevailing lithography tools. | 02-04-2010 |
| 20100264492 | Semiconductor on Insulator Semiconductor Device and Method of Manufacture - A semiconductor on insulator semiconductor device has metal or silicide source and drain contact regions ( | 10-21-2010 |
| 20110018064 | SRAM CELL COMPRISING FINFETS - An SRAM finFET cell includes fins ( | 01-27-2011 |
| 20110049639 | INTEGRATED CIRCUIT MANUFACTURING METHOD AND INTEGRATED CIRCUIT - A method is disclosed of manufacturing an integrated circuit. The method comprises providing a substrate ( | 03-03-2011 |
Gerben Doornbos, Kessel-L9 BE
| Patent application number | Description | Published |
|---|---|---|
| 20100068859 | METHOD OF MANUFACTURING A FET GATE - A method of manufacturing a FET gate with a plurality of materials includes depositing a dummy region | 03-18-2010 |
Gerben Doornbos, Leuven BE
| Patent application number | Description | Published |
|---|---|---|
| 20090114950 | Semiconductor Device and Method of Manufacturing such a Device - The invention relates to a semiconductor device ( | 05-07-2009 |
| 20100006945 | FINFET DRIVE STRENGTH MODIFICATION - A method and circuit in which the drive strength of a FinFET transistor can be selectively modified, and in particular can be selectively reduced, by omitting the LDD extension formation in the source and/or in the drain of the FinFET. | 01-14-2010 |
Gerben Doornbos, Heverlee BE
| Patent application number | Description | Published |
|---|---|---|
| 20080230824 | Double Gate Non-Volatile Memory Device and Method of Manufacturing - The present invention relates to a non-volatile memory device on a substrate layer comprising semiconductor source and drain regions, a semiconductor channel region, a charge storage stack and a control gate; the channel region being fin-shaped having two sidewall portions and a top portion, and extending between the source region and the drain region; the charge storage stack being positioned between the source and drain regions and extending over the fin-shaped channel, substantially perpendicularly to the length direction of the fin-shaped channel; the control gate being in contact with the charge storage stack, wherein—an access gate is provided adjacent to one sidewall portion and separated therefrom by an intermediate gate oxide layer, and—the charge storage stack contacts the fin-shaped channel on the other sidewall portion and is separated from the channel by the intermediate gate oxide layer. | 09-25-2008 |
| 20090073746 | STATIC RANDOM ACCESS MEMORY CELL - A static random access memory means is provided. The SRAM memory means comprises a first pass-gate FET (T | 03-19-2009 |
| 20090209092 | SEIMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE THEREOF - A FinFET and methods for its manufacture are provided. The method of the invention provides an elegant process for manufacturing FinFETs with separated gates. It is compatible with a wide range of dielectric materials and gate electrode materials, providing that the gate electrode material(s) can be deposited conformally. Provision of at least one upstanding structure (or “dummy fin”) ( | 08-20-2009 |
Gerben Doornbos, Kessel BE
| Patent application number | Description | Published |
|---|---|---|
| 20110169101 | Fin Field Effect Transistor (FINFET) - A Fin FET whose fin ( | 07-14-2011 |