| Patent application number | Description | Published |
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| 20090028574 | SELF-TESTING OPTICAL TRANSCEIVER - Systems and methods for an optical transceiver module to perform one or more diagnostic self-tests without the assistance of a host computing system. The optical transceiver module includes at least one processor, a persistent memory and a system memory. The persistent memory, which is coupled to the at least one processor, contains microcode. The microcode is loaded from the persistent memory to the system memory and executed by the at least one processor. The executed microcode causes the optical transceiver module to perform one or more diagnostic self-tests. The diagnostic result data of the one or more diagnostic self-tests is then stored in the persistent memory and is formatted for analysis. The formatted data may then be analyzed to ascertain the response of the optical transceiver to changes in its test environment. | 01-29-2009 |
| 20090067848 | LIMITED LIFE TRANSCEIVER - Systems and methods for an optical transceiver module to limit the amount of time the optical transceiver module is allowed to operate. The optical transceiver module includes at least one processor, a persistent memory and a system memory. The persistent memory, which is coupled to the at least one processor, contains microcode. The microcode is loaded from the persistent memory to the system memory and executed by the at least one processor. The executed microcode causes the optical transceiver module to detect the amount of time that the optical transceiver has been operating. The optical transceiver module then determines if the detected amount of operating time is in excess of a predetermined amount of operating time. If the detected operating time is in excess of the predetermined amount of operating time, the optical transceiver module causes itself to become non-operational. The optical transceiver module may then report its operational status. | 03-12-2009 |
| 20090138709 | OPTICAL TRANSCEIVER WITH VENDOR AUTHENTICATION - An optical receiver comprising at least one processor and a memory including at least one of an encryption key or a decryption key and at least one of encryption microcode or decryption microcode that includes processor-executable instructions that, when executed by the at least one processor, cause the optical transceiver to perform the following: an act of performing an encryption or decryption operation on data received from a host computing system to thereby authenticate the optical transceiver. | 05-28-2009 |
| 20100254710 | EARLY SELF-VALIDATION OF PERSISTENT MEMORY DURING BOOT IN AN OPTICAL TRANSCEIVER - An operational optical transceiver configured to self-validate a boot image loaded from the persistent memory early in the boot process. The optical transceiver includes a persistent memory, a controller, and a system memory. The controller initializes the boot process and begins to load information from the persistent memory to the system memory. Next, the controller detects early in the boot process boot image verification data in the information being sent to the system memory. The controller then determines if the boot image verification data has an expected value. If the verification data includes the expected value, the controller continues the boot process. If the verification data does not include the expected value, the controller will retry the boot process a predetermined number of times and will enter a default operational state if the expected value is not detected while retrying the boot process the predetermined number of times. | 10-07-2010 |
| 20110010576 | MICROCODE CONFIGURABLE FREQUENCY CLOCK - A microcode configurable frequency clock that may be used to control the speed of high speed comparison in an operational optical transceiver. The frequency clock includes a memory and a logic circuit. The memory receives microcode generated data relating to the desired speed of comparison. The logic circuit is configured to receive an input clock signal and to produce an output clock signal by frequency dividing the input signal based on the microcode generated data. The output clock is used to control the speed of comparison in the optical transceiver. | 01-13-2011 |
| 20110020007 | INTER-TRANSCEIVER MODULE COMMUNICATION FOR OPTIMIZATION OF LINK BETWEEN TRANSCEIVERS - Two or more optical transceivers coupled to each other by an optical link to optimize communication over the optical link. A first transceiver generates electrical data that represents an operational parameter for optimization. The transceiver then converts the electrical data into an optical signal and transmits the optical signal over the optical link to a second transceiver. The second transceiver recovers the electrical data from the optical signal and uses the recovered electrical data to change characteristics of the optical signal transmitted by the second transceiver. | 01-27-2011 |
| 20120134680 | INTER-TRANSCEIVER MODULE COMMUNICATION FOR FIRMWARE UPGRADE - An operational optical transceiver configured to update operational firmware using an optical link of the transceiver. The optical transceiver includes at least one processor and a system memory capable of receiving firmware. The optical transceiver receives an optical signal over the optical link containing the update firmware. The optical transceiver then recovers the firmware from the optical signal. Finally, the optical transceiver provides to the system memory the recovered firmware, which when executed by the at least one processor alters the operation of the transceiver. | 05-31-2012 |
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| 20090174434 | DESIGN METHOD AND ARCHITECTURE FOR POWER GATE SWITCH PLACEMENT - A design method places power gates or switch cells using unoccupied locations of logic cell rows. Two types of such switch cells, filler switches and sealer switches, may be provided using the unoccupied locations. In one embodiment, virtual ground voltage references to the logic cells are routed to their associated switch cells. Because conventional standard cell design and placement techniques achieve only a placement density or utilization between 70-80% (i.e., unoccupied space constitutes between 20 to 30% of the available space in each row of logic cells), by placing the power gate cells in the unoccupied space, the method does not increase the silicon real estate requirement even though the power gate cells are introduced into the design. Optimization techniques may be applied to achieve proper sizing and distribution of power gate cells, so as to avoid a performance penalty due to the power gate cells. In one embodiment, fine-grained power gating is achieved by selectively providing non-power-gated logic cells among power-gated logic cells. | 07-09-2009 |
| 20090300569 | DESIGN METHOD AND ARCHITECTURE FOR POWER GATE SWITCH PLACEMENT - A design method places power gates or switch cells using unoccupied locations of logic cell rows. Two types of such switch cells, filler switches and sealer switches, may be provided using the unoccupied locations. In one embodiment, virtual ground voltage references to the logic cells are routed to their associated switch cells. Because conventional standard cell design and placement techniques achieve only a placement density or utilization between 70-80% (i.e., unoccupied space constitutes between 20 to 30% of the available space in each row of logic cells), by placing the power gate cells in the unoccupied space, the method does not increase the silicon real estate requirement even though the power gate cells are introduced into the design. Optimization techniques may be applied to achieve proper sizing and distribution of power gate cells, so as to avoid a performance penalty due to the power gate cells. In one embodiment, fine-grained power gating is achieved by selectively providing non-power-gated logic cells among power-gated logic cells. | 12-03-2009 |
| 20100063761 | Clock Jitter Analysis - A tool and a method analyze variations in signal timing, especially timing in a clock signal, commonly known as “clock Jitter.” The tool and method provide advantages over conventional analysis approaches, such as comprehensive coverage of all clocks in a design, taking into account all signal coupling effects, ease of use, ability to automatically identify individual jitter sources, and efficient use of computing resources. | 03-11-2010 |
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| 20080295330 | Method and process for manufacturing a terminal block - A method of manufacturing a terminal block for a telecommunication cable comprising the steps of providing a preformed substrate member comprising a podium member, at least one electrical connector and at least one insulated electrical wire attached to an electrical contact positioned within the at least one electrical connector; placing the preformed substrate member in a mold; and injecting a dielectric material into the mold containing the podium member to form an overmolded terminal block, wherein the dielectric material covers the at least one insulated electrical wire and a portion of the electrical contact positioned within the at least one electrical connector. | 12-04-2008 |
| 20090304341 | SEALING GLAND SYSTEM - A sealing gland system having an upper half, a lower half, and a sealing material positioned between the upper and lower halves. Each of the upper and lower halves and the sealing material has at least one opening extending therethrough, and wherein the sealing material forms a seal around at least one cable extending through the sealing material upon compression thereof. | 12-10-2009 |
| 20100269340 | METHOD AND PROCESS FOR MANUFACTURING A TERMINAL BLOCK - A method of manufacturing a terminal block for a telecommunication cable comprising the steps of providing a preformed substrate member comprising a podium member, at least one electrical connector and at least one insulated electrical wire attached to an electrical contact positioned within the at least one electrical connector; placing the preformed substrate member in a mold; and injecting a dielectric material into the mold containing the podium member to form an overmolded terminal block, wherein the dielectric material covers the at least one insulated electrical wire and a portion of the electrical contact positioned within the at least one electrical connector. | 10-28-2010 |
| 20110268416 | SEALING GLAND SYSTEM - A sealing gland system having an upper half, a lower half, and a sealing material positioned between the upper and lower halves. Each of the upper and lower halves and the sealing material has at least one opening extending therethrough, and wherein the sealing material forms a seal around at least one cable extending through the sealing material upon compression thereof. | 11-03-2011 |
| 20110272894 | SEALING GLAND SYSTEM - A sealing gland system having an upper half, a lower half, and a sealing material positioned between the upper and lower halves. Each of the upper and lower halves and the sealing material has at least one opening extending therethrough, and wherein the sealing material forms a seal around at least one cable extending through the sealing material upon compression thereof. | 11-10-2011 |
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| 20090243284 | Fluid Transfer Assemblies and Related Methods - An assembly includes a first polymeric connector having a first passageway and a second passageway fixed relative to the first passageway; a first polymeric conduit having a third passageway in fluid communication with the first passageway; and a polymeric member extending over a gap between the first connector and the first conduit and at least portions of outer surfaces of the first connector and the first conduit. A method of attaching a first polymeric connector having a first passageway and a second passageway fixed relative to the first passageway, and a first polymeric conduit having a third passageway, the method includes attaching the first polymeric connector to the first polymeric conduit with a polymeric member extending over at least portions of outer surfaces of the first connector and the first conduit. The first passageway is in fluid communication with the third passageway. | 10-01-2009 |
| 20110241262 | FLEXIBLE TUBING MATERIAL AND METHOD OF FORMING THE MATERIAL - A flexible tubing material includes a radiation crosslinked blend of a first elastomeric polymer including a styrenic thermoplastic elastomer, an ethylene vinyl acetate elastomer, a polyolefin elastomer with a second elastomeric polymer including a polyolefin elastomer, a diene elastomer, or combination thereof, with the proviso that the first elastomeric polymer and the second elastomeric polymer are different. In an embodiment, a method of making a material includes providing the first elastomeric polymer, providing the second elastomeric polymer, blending the first elastomeric polymer and the second elastomeric polymer, extruding or injection molding the blend, and crosslinking the blend with radiation. | 10-06-2011 |
