Patent application number | Description | Published |
20090257265 | Multilevel nonvolatile memory device containing a carbon storage material and methods of making and using same - A nonvolatile memory cell includes a steering element located in series with a storage element. The storage element includes a carbon material and the memory cell includes a rewritable cell having multiple memory levels. | 10-15-2009 |
20090286370 | Multi-State Non-Volatile Integrated Circuit Memory Systems that Employ Dielectric Storage Elements - Non-volatile memory cells store a level of charge corresponding to the data being stored in a dielectric material storage element that is sandwiched between a control gate and the semiconductor substrate surface over channel regions of the memory cells. More than two memory states are provided by one of more than two levels of charge being stored in a common region of the dielectric material. More than one such common region may be included in each cell. In one form, two such regions are provided adjacent source and drain diffusions in a cell that also includes a select transistor positioned between them. In another form, NAND arrays of strings of memory cells store charge in regions of a dielectric layer sandwiched between word lines and the semiconductor substrate. | 11-19-2009 |
20100259960 | Three-Dimensional Array of Re-Programmable Non-Volatile Memory Elements Having Vertical Bit Lines - A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes. | 10-14-2010 |
20100259961 | Three-Dimensional Array of Re-Programmable Non-Volatile Memory Elements Having Vertical Bit Lines and a Double-Global-Bit-Line Architecture - A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which the memory elements of all planes are connected is oriented vertically from the substrate and through the plurality of planes. A double-global-bit-line architecture provides a pair of global bit lines for each bit lines for accessing a row of memory elements in parallel. A first one of each pair allows the local bit lines of the row to be sensed while a second one of each pair allows local bit lines in an adjacent row to be set to a definite voltage so as to eliminate leakage currents between adjacent rows of local bit lines. | 10-14-2010 |
20100259962 | Three-Dimensional Array of Re-Programmable Non-Volatile Memory Elements Having Vertical Bit Lines and a Single-Sided Word Line Architecture - A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which the memory elements of all planes are connected is oriented vertically from the substrate and through the plurality of planes. A single-sided word line architecture provides a word line exclusively for each row of memory elements instead of sharing one word line between two rows of memory elements thereby avoids linking the memory element across the array across the word lines. While the row of memory elements is also being accessed by a corresponding row of local bit lines, there is no extension of coupling between adjacent rows of local bit lines and therefore leakage currents beyond the word line. | 10-14-2010 |
20110089391 | PUNCH-THROUGH DIODE STEERING ELEMENT - A storage system and method for forming a storage system that uses punch-through diodes as a steering element in series with a reversible resistivity-switching element is described. The punch-through diode allows bipolar operation of a cross-point memory array. The punch-through diode may have a symmetrical non-linear current/voltage relationship. The punch-through diode has a high current at high bias for selected cells and a low leakage current at low bias for unselected cells. Therefore, it is compatible with bipolar switching in cross-point memory arrays having resistive switching elements. The punch-through diode may be a N+/P−/N+ device or a P+/N−/P+ device. | 04-21-2011 |
20110280076 | JUNCTIONLESS TFT NAND FLASH MEMORY - A non-volatile memory device includes at least one junctionless transistor and a storage region. The junctionless transistor includes a junctionless, heavily doped semiconductor channel having two dimensions less than 100 nm. | 11-17-2011 |
20110297912 | Non-Volatile Memory Having 3d Array of Read/Write Elements with Vertical Bit Lines and Laterally Aligned Active Elements and Methods Thereof - A three-dimensional array of memory elements is formed across multiple layers of planes positioned at different distances above a semiconductor substrate. The memory elements reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The three-dimensional array includes a two-dimensional array of pillar lines from the substrate through the multiple layers of planes which together with arrays of word lines on each plane are used to access the memory elements. The memory elements of the multiple layers are formed simultaneously in an orientation parallel to the substrate thereby reducing processing cost. In another aspect, a diode is formed in series with each memory element to reduce current leakage. The diode is incorporated within a pillar line acting as a bit line without taking up additional space. | 12-08-2011 |
20110299314 | Non-Volatile Memory Having 3d Array of Read/Write Elements with Efficient Decoding of Vertical Bit Lines and Word Lines - A three-dimensional array of memory elements is formed across multiple layers of planes positioned at different distances above a semiconductor substrate. The memory elements reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The three-dimensional array includes a two-dimensional array of pillar lines from the substrate through the multiple layers of planes. A first set of pillar lines acts as local bit lines for accessing the memory elements together with an array of word lines on each plane. A second set of pillar lines is connected to the word lines. An array of metal lines on the substrate is switchable connected to the pillar lines to provide access to the first and second sets of pillar lines, thereby to provide access respectively to the bit lines and word lines of the three-dimensional array. | 12-08-2011 |
20110299340 | Non-Volatile Memory Having 3d Array of Read/Write Elements and Read/Write Circuits and Method Thereof - A three-dimensional array is especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which the memory elements of all planes are connected is oriented vertically from the substrate and through the plurality of planes. During sensing, to compensate for word line resistance, a sense amplifier references a stored reference value during sensing of a memory element at a given location of the word line. A layout with a row of sense amplifiers between two memory arrays is provided to facilitate the referencing. A selected memory element is reset without resetting neighboring ones when it is subject to a bias voltage under predetermined conditions. | 12-08-2011 |
20110310655 | Composition Of Memory Cell With Resistance-Switching Layers - A memory device in a 3-D read and write memory includes memory cells. Each memory cell includes a resistance-switching memory element (RSME) in series with a steering element. The RSME has first and second resistance-switching layers on either side of a conductive intermediate layer, and first and second electrodes at either end of the RSME. The first and second resistance-switching layers can both have a bipolar or unipolar switching characteristic. In a set or reset operation of the memory cell, an ionic current flows in the resistance-switching layers, contributing to a switching mechanism. An electron flow, which does not contribute to the switching mechanism, is reduced due to scattering by the conductive intermediate layer, to avoid damage to the steering element. Particular materials and combinations of materials for the different layers of the RSME are provided. | 12-22-2011 |
20120001249 | ULTRAHIGH DENSITY VERTICAL NAND MEMORY DEVICE & METHOD OF MAKING THEREOF - Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel. | 01-05-2012 |
20120120709 | Transistor Driven 3D Memory - A nonvolatile memory device with a first conductor extending in a first direction and a semiconductor element above the first conductor. The semiconductor element includes a source, a drain and a channel of a field effect transistor (JFET or MOSFET). The nonvolatile memory device also includes a second conductor above the semiconductor element, the second conductor extending in a second direction. The nonvolatile memory device also includes a resistivity switching material disposed between the first conductor and the semiconductor element or between the second conductor and the semiconductor element. The JFET or MOSFET includes a gate adjacent to the channel, and the MOSFET gate being self-aligned with the first conductor. | 05-17-2012 |
20120120710 | MEMORY SYSTEM WITH REVERSIBLE RESISTIVITY-SWITCHING USING PULSES OF ALTERNATRIE POLARITY - A memory system includes a plurality of non-volatile storage elements that each comprise a diode (or other steering device) in series with reversible resistance-switching material. One or more circuits in the memory system program the non-volatile storage elements by changing the reversible resistance-switching material of one or more non-volatile storage elements to a first resistance state. The memory system can also change the reversible resistance-switching material of one or more of the non-volatile storage elements from the first resistance state to a second resistance state by applying one or more pairs of opposite polarity voltage conditions (e.g., pulses) to the respective diodes (or other steering devices) such that current flows in the diodes (or other steering devices) without operating the diodes (or other steering devices) in breakdown condition. | 05-17-2012 |
20120120711 | MEMORY SYSTEM WITH REVERSIBLE RESISTIVITY-SWITCHING USING PULSES OF ALTERNATRIE POLARITY - A memory system includes a plurality of non-volatile storage elements that each comprise a diode (or other steering device) in series with reversible resistance-switching material. One or more circuits in the memory system program the non-volatile storage elements by changing the reversible resistance-switching material of one or more non-volatile storage elements to a first resistance state. The memory system can also change the reversible resistance-switching material of one or more of the non-volatile storage elements from the first resistance state to a second resistance state by applying one or more pairs of opposite polarity voltage conditions (e.g., pulses) to the respective diodes (or other steering devices) such that current flows in the diodes (or other steering devices) without operating the diodes (or other steering devices) in breakdown condition. | 05-17-2012 |
20120147649 | Non-Volatile Memory Having 3d Array of Read/Write Elements with Low Current Structures and Methods Thereof - A three-dimensional array read/write (R/W) memory elements is formed across multiple layers of planes positioned at different distances above a semiconductor substrate. It is preferable to operate the R/W elements with low current and high resistive states. The resistance of these resistive states depends also on the dimension of the R/W elements and is predetermined by the process technology. A sheet electrode in series with the R/W element and a method of forming it provide another degree of freedom to adjust the resistance of the R/W memory element. The thickness of the sheet electrode is adjusted to obtain a reduced cross-sectional contact in the circuit path from the word line to the bit line. This allows the R/W memory element to have a much increased resistance and therefore to operate with much reduced currents. The sheet electrode is formed with little increase in cell size. | 06-14-2012 |
20120147650 | Non-Volatile Memory Having 3D Array of Read/Write Elements with Vertical Bit Lines and Select Devices and Methods Thereof - A three-dimensional memory is formed as an array of memory elements that are formed across multiple layers of planes positioned at different distances above a semiconductor substrate. The memory elements reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The three-dimensional array includes a two-dimensional array of pillar lines acting as local vertical bit lines through the multiple layers of planes which together with arrays of word lines on each plane are used to access the memory elements. The three-dimensional memory is formed over a CMOS substrate with an intermediate pillar select layer. The pillar select layer is formed with a plurality of pillar select devices which are switching transistors formed outside the CMOS and serve to switch selected rows of pillar lines to corresponding metal lines on the substrate. | 06-14-2012 |
20120302029 | PUNCH-THROUGH DIODE STEERING ELEMENT - A storage system and method for forming a storage system that uses punch-through diodes as a steering element in series with a reversible resistivity-switching element is described. The punch-through diode allows bipolar operation of a cross-point memory array. The punch-through diode may have a symmetrical non-linear current/voltage relationship. The punch-through diode has a high current at high bias for selected cells and a low leakage current at low bias for unselected cells. Therefore, it is compatible with bipolar switching in cross-point memory arrays having resistive switching elements. The punch-through diode may be a N+/P−/N+ device or a P+/N−/P+ device. | 11-29-2012 |
20130095646 | ULTRAHIGH DENSITY VERTICAL NAND MEMORY DEVICE AND METHOD OF MAKING THEREOF - Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel. | 04-18-2013 |
20130121078 | THREE-DIMENSIONAL ARRAY OF RE-PROGRAMMABLE NON-VOLATILE MEMORY ELEMENTS HAVING VERTICAL BIT LINES AND A SINGLE-SIDED WORD LINE ARCHITECTURE - A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which the memory elements of all planes are connected is oriented vertically from the substrate and through the plurality of planes. A single-sided word line architecture provides a word line exclusively for each row of memory elements instead of sharing one word line between two rows of memory elements thereby avoids linking the memory element across the array across the word lines. While the row of memory elements is also being accessed by a corresponding row of local bit lines, there is no extension of coupling between adjacent rows of local bit lines and therefore leakage currents beyond the word line. | 05-16-2013 |
20130188431 | TEMPERATURE COMPENSATION OF CONDUCTIVE BRIDGE MEMORY ARRAYS - Methods for operating a semiconductor memory array including dynamically adjusting control line voltages (e.g., unselected word line or unselected bit line voltages) based on one or more array conditions associated with the semiconductor memory array are described. The one or more array conditions may include a temperature associated with the semiconductor memory array or a particular number of write cycles associated with the semiconductor memory array. In some embodiments, an intermediate voltage is generated based on the one or more array conditions and applied to the unselected word lines and the unselected bit lines of the semiconductor memory array. The one or more intermediate voltages may be generated such that a first voltage difference across unselected memory cells sharing a selected word line is different from a second voltage difference across other unselected memory cells sharing a selected bit line based on the one or more array conditions. | 07-25-2013 |
20130229846 | Memories with Cylindrical Read/Write Stacks - A three-dimensional memory is formed as an array of memory elements across multiple layers positioned at different distances above a semiconductor substrate. Cylindrical stacks of memory elements are formed where a cylindrical opening has read/write material deposited along its wall, and a cylindrical vertical bit line formed along its central axis. Memory elements formed on either side of such a cylinder may include sheet electrodes that extend into the read/write material. | 09-05-2013 |
20130237024 | ULTRAHIGH DENSITY VERTICAL NAND MEMORY DEVICE AND METHOD OF MAKING THEREOF - Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel. | 09-12-2013 |
20130336038 | NON-VOLATILE MEMORY HAVING 3D ARRAY ARCHITECTURE WITH STAIRCASE WORD LINES AND VERTICAL BIT LINES AND METHODS THEREOF - In a 3D nonvolatile memory with memory elements arranged in a three-dimensional pattern defined by rectangular coordinates having x, y and z-directions and with a plurality of parallel planes from a bottom plane to a top plane stacked in the z-direction over a semiconductor substrate; a plurality of local bit lines elongated in the z-direction through the plurality of layers and arranged in a two-dimensional rectangular array of bit line pillars having rows in the x-direction and columns in the y-direction; the 3D nonvolatile memory further having a plurality of staircase word lines spaced apart in the y-direction and between and separated from the plurality of bit line pillars at a plurality of crossings, individual staircase word lines each having a series of alternating steps and risers elongated respectively in the x-direction and z-direction traversing across the plurality of planes in the z-direction with a segment in each plane. | 12-19-2013 |
20140001533 | NAND Memory Device Containing Nanodots and Method of Making Thereof | 01-02-2014 |
20140001535 | Non-Volatile Memory Structure Containing Nanodots and Continuous Metal Layer Charge Traps and Method of Making Thereof | 01-02-2014 |
20140022848 | NON-VOLATILE MEMORY HAVING 3D ARRAY OF READ/WRITE ELEMENTS AND READ/WRITE CIRCUITS AND METHOD THEREOF - A three-dimensional array is especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which the memory elements of all planes are connected is oriented vertically from the substrate and through the plurality of planes. During sensing, to compensate for word line resistance, a sense amplifier references a stored reference value during sensing of a memory element at a given location of the word line. A layout with a row of sense amplifiers between two memory arrays is provided to facilitate the referencing. A selected memory element is reset without resetting neighboring ones when it is subject to a bias voltage under predetermined conditions. | 01-23-2014 |
20140029356 | TEMPERATURE COMPENSATION OF CONDUCTIVE BRIDGE MEMORY ARRAYS - Methods for operating a semiconductor memory array including dynamically adjusting control line voltages (e.g., unselected word line or unselected bit line voltages) based on one or more array conditions associated with the semiconductor memory array are described. The one or more array conditions may include a temperature associated with the semiconductor memory array or a particular number of write cycles associated with the semiconductor memory array. In some embodiments, an intermediate voltage is generated based on the one or more array conditions and applied to the unselected word lines and the unselected bit lines of the semiconductor memory array. The one or more intermediate voltages may be generated such that a first voltage difference across unselected memory cells sharing a selected word line is different from a second voltage difference across other unselected memory cells sharing a selected bit line based on the one or more array conditions. | 01-30-2014 |
20140045307 | ULTRAHIGH DENSITY VERTICAL NAND MEMORY DEVICE AND METHOD OF MAKING THEREOF - Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel. | 02-13-2014 |
20140175530 | THREE DIMENSIONAL NAND DEVICE WITH SILICIDE CONTAINING FLOATING GATES AND METHOD OF MAKING THEREOF - A method of making a monolithic three dimensional NAND string, including providing a stack of alternating first material layers and second material layers different from the first material layer over a substrate, the stack comprising at least one opening containing a charge storage material comprising a silicide layer, a tunnel dielectric on the charge storage material in the at least one opening, and a semiconductor channel on the tunnel dielectric in the at least one opening, selectively removing the second material layers without removing the first material layers from the stack and forming control gates between the first material layers. | 06-26-2014 |
20140252447 | Nanodot-Enhanced Hybrid Floating Gate for Non-Volatile Memory Devices - A memory device and a method of making a memory device that includes a semiconductor channel, a tunnel dielectric layer located over the semiconductor channel, a floating gate located over the tunnel dielectric layer, the floating gate comprising a continuous layer of an electrically conductive material and at least one protrusion of an electrically conductive material facing the tunnel dielectric layer and electrically shorted to the continuous layer, a blocking dielectric region located over the floating gate, and a control gate located over the blocking dielectric layer. | 09-11-2014 |
20140254231 | 3D Non-Volatile Memory Having Low-Current Cells and Methods - A 3D array of nonvolatile memory has each read/write element accessed at a crossing between a word line and a bit line. The read/write element forms a tubular electrode having an outside shell of R/W material enclosing an oxide core. In a rectangular form, one side of the electrode contacts the word line and another side contacts the bit line. The thickness of the shell rather than its surface areas in contact with the word line and bit line determines the conduction cross-section and therefore the resistance. By adjusting the thickness of the shell, independent of its contact area with either the word line or bit line, each read/write element can operate with a much increased resistance and therefore much reduced current. Processes to manufacture a 3D array with such tubular R/W elements 3D array are also described. | 09-11-2014 |
20140335671 | NON-VOLATILE MEMORY HAVING 3D ARRAY OF READ/WRITE ELEMENTS WITH VERTICAL BIT LINES AND SELECT DEVICES AND METHODS THEREOF - A three-dimensional memory is formed as an array of memory elements that are formed across multiple layers of planes positioned at different distances above a semiconductor substrate. The memory elements reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The three-dimensional array includes a two-dimensional array of pillar lines acting as local vertical bit lines through the multiple layers of planes which together with arrays of word lines on each plane are used to access the memory elements. The three-dimensional memory is formed over a CMOS substrate with an intermediate pillar select layer. The pillar select layer is formed with a plurality of pillar select devices which are switching transistors formed outside the CMOS and serve to switch selected rows of pillar lines to corresponding metal lines on the substrate. | 11-13-2014 |
20150036414 | SHARED-GATE VERTICAL-TFT FOR VERTICAL BIT LINE ARRAY - A non-volatile storage device comprises: a substrate; a monolithic three dimensional array of memory cells; word lines connected to the memory cells; global bit lines; vertical bit lines connected to the memory cells; and a plurality of double gated vertically oriented select devices. The double gated vertically oriented select devices are connected to the vertical bit lines and the global bit lines so that when the double gated vertically oriented select devices are activated the vertical bit lines are in communication with the global bit lines. Each double gated vertically oriented select device has two gates that are offset from each other with respect to distance to the substrate. Both gates for the double gated vertically oriented select device need be in an “on” condition for the double gated vertically oriented select devices to be activated. | 02-05-2015 |
20150072488 | THREE DIMENSIONAL NAND DEVICE WITH SILICIDE CONTAINING FLOATING GATES AND METHOD OF MAKING THEREOF - A method of making a monolithic three dimensional NAND string, including providing a stack of alternating first material layers and second material layers different from the first material layer over a substrate, the stack comprising at least one opening containing a charge storage material comprising a silicide layer, a tunnel dielectric on the charge storage material in the at least one opening, and a semiconductor channel on the tunnel dielectric in the at least one opening, selectively removing the second material layers without removing the first material layers from the stack and forming control gates between the first material layers. | 03-12-2015 |