| Patent application number | Description | Published |
|---|
| 20080206931 | NONVOLATILE MEMORY ELEMENT AND PRODUCTION METHOD THEREOF AND STORAGE MEMORY ARRANGEMENT - A nonvolatile memory element and associated production methods and memory element arrangements are presented. The nonvolatile memory element has a changeover material and a first and second electrically conductive electrode present at the changeover material. To reduce a forming voltage, a first electrode has a field amplifier structure for amplifying a field strength of an electric field generated by a second electrode in a changeover material. The field amplifier structure is a projection of the electrodes which projects into the changeover material. The memory element arrangement has multiple nonvolatile memory elements which are arranged in matrix form and can be addressed via bit lines arranged in column form and word lines arranged in row form. | 08-28-2008 |
| 20080296662 | Discrete Trap Memory (DTM) Mediated by Fullerenes - A discrete trap memory, comprising a silicon substrate layer, a bottom oxide layer on the silicon substrate layer, a Fullerene layer on the bottom oxide layer, a top oxide layer on the Fullerene layer, and a gate layer on the top oxide layer; wherein the Fullerene layer comprises spherical, elliptical or endohedral Fullerenes that act as charge traps. | 12-04-2008 |
| 20090020800 | Semiconductor Device and Method of Making Same - A semiconductor device and method of making a semiconductor device are disclosed. A semiconductor body, a floating gate poly and a source/drain region are provided. A metal interconnect region with a control gate node is provided that capacitively couples to the floating gate poly. | 01-22-2009 |
| 20090176358 | Discrete Trap Memory (DTM) Mediated by Fullerenes - A discrete trap memory, comprising a silicon substrate layer, a bottom oxide layer on the silicon substrate layer, a Fullerene layer on the bottom oxide layer, a top oxide layer on the Fullerene layer, and a gate layer on the top oxide layer; wherein the Fullerene layer comprises spherical, elliptical or endohedral Fullerenes that act as charge traps. | 07-09-2009 |
| 20100006925 | NON-VOLATILE TWO TRANSISTOR MEMORY CELL AND METHOD FOR PRODUCING THE SAME - The invention relates to a nonvolatile two-transistor semiconductor memory cell and an associated fabrication method, source and drain regions ( | 01-14-2010 |
| 20100129972 | BIT LINE STRUCTURE AND METHOD FOR THE PRODUCTION THEREOF - A bit line structure and associated fabrication method are provided for a semiconductor element or circuit arrangement. The bit line structure contains a surface bit line and a buried bit line. The buried bit line is formed in an upper section of a trench and is connected to an associated first doping region via a first connection layer. A first trench filling layer, which is insulated from the buried bit line by a second trench insulating layer, is situated in a lower section of the trench. | 05-27-2010 |
| 20110003457 | SEMICONDUCTOR COMPONENT WITH TRENCH INSULATION AND CORRESPONDING PRODUCTION METHOD - The invention relates to a semiconductor component with trench isolation and to an associated fabrication method, a trench isolation (STI, TTI) having a deep isolation trench with a covering insulation layer ( | 01-06-2011 |
| 20110159661 | Nonvolatile Memory Element and Production Method Thereof and Storage Memory Arrangement - A nonvolatile memory element and associated production methods and memory element arrangements are presented. The nonvolatile memory element has a changeover material and a first and second electrically conductive electrode present at the changeover material. To reduce a forming voltage, a first electrode has a field amplifier structure for amplifying a field strength of an electric field generated by a second electrode in a changeover material. The field amplifier structure is a projection of the electrodes which projects into the changeover material. The memory element arrangement has multiple nonvolatile memory elements which are arranged in matrix form and can be addressed via bit lines arranged in column form and word lines arranged in row form. | 06-30-2011 |
