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Gebara
Edward Gebara US
| Patent application number | Description | Published |
|---|---|---|
| 20100197233 | Method and System for Automatic Control in an Interference Cancellation Device - Signals propagating on an aggressor communication channel can cause detrimental interference in a victim communication channel. A signal processing circuit can generate an interference cancellation signal that, when applied to the victim communication channel, cancels the detrimental interference. The signal processing circuit can dynamically adjust or update two or more aspects of the interference cancellation signal, such as an amplitude or gain parameter and a phase or delay parameter. Via the dynamic adjustments, the signal processing circuit can adapt to changing conditions, thereby maintaining an acceptable level of interference cancellation in a fluctuating operating environment. A control circuit that implements the parametric adjustments can have at least two modes of operation, one for adjusting the amplitude parameter and one for adjusting the phase parameter. The modes can be selectable or can be intermittently available, for example. | 08-05-2010 |
Edward Gebara, Atlanta, GA US
| Patent application number | Description | Published |
|---|---|---|
| 20090170438 | Method and system for reducing signal interference - Signals propagating on an aggressor communication channel can cause interference in a victim communication channel. A sensor coupled to the aggressor channel can obtain a sample of the aggressor signal. The sensor can be integrated with or embedded in a system, such as a flex circuit or a circuit board, that comprises the aggressor channel. The sensor can comprise a dedicated conductor or circuit trace that is near an aggressor conductor, a victim conductor, or an EM field associated with the interference. An interference compensation circuit can receive the sample from the sensor. The interference compensation circuit can have at least two operational modes of operation. In the first mode, the circuit can actively generate or output a compensation signal that cancels, corrects, or suppresses the interference. The second mode can be a standby, idle, power-saving, passive, or sleep mode. | 07-02-2009 |
| 20100027709 | Method And System For Slicing A Communication Signal - A slicer can receive a communication signal having a level or amplitude that is between two discrete levels of a multilevel digital communication scheme. The slicer can compare the communication signal to a plurality of references such that multiple comparisons proceed essentially in parallel. A summation node can add the results of the comparisons to provide an output signal set to one of the discrete levels. The slicer can process the communication signal and provide the output signal on a symbol-by-symbol basis. A decision feedback equalizer (“DFE”) can comprise the slicer. A feedback circuit of the DFE can delay and scale the output signal and apply the delayed and scaled signal to the communication signal to reduce intersymbol interference (“ISI”). | 02-04-2010 |
Fadi Hikmat Gebara, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20100001766 | SYSTEM TO EVALUATE A VOLTAGE IN A CHARGE PUMP AND ASSOCIATED METHODS - A system to evaluate a voltage in a charge pump may include a transistor, and a transistor drain carried by the transistor with the transistor drain receiving a reference current. The system may also include a transistor gate carried by the transistor and connected to the transistor drain. The system may further include an additional transistor and an additional transistor gate carried by the additional transistor and connected to the transistor gate. The system may additionally include an additional transistor drain to receive the reference current mirrored from the additional transistor. | 01-07-2010 |
Gabriel Gebara, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20090028422 | Systems and Methods for Detecting Watermark Formations on Semiconductor Wafers - Systems and methods for detecting watermark formations on semiconductor wafers are described. In one embodiment, a method comprises providing a semiconductor wafer having at least one watermark sensitive region fabricated thereon, subjecting the wafer to a wet processing step, enhancing a susceptibility to detection of at least one watermark formation created on the at least one watermark sensitive region, and detecting the at least one watermark formation. In another embodiment, a method comprises growing a first oxide layer on a surface of a semiconductor wafer, patterning a watermark sensitive structure on the first oxide layer, depositing a silicon layer over the first oxide layer, doping a region of the silicon layer over the watermark sensitive structure with an impurity to create a watermark sensitive region that is prone to retaining watermark formations as result of a wet processing step, and growing a second oxide layer over the silicon layer. | 01-29-2009 |
| 20100081278 | Methods for Nanoscale Feature Imprint Molding - Methods for fabricating nanoscale features are disclosed. One technique involves depositing onto a substrate, where the first layer may be a silicon layer and may subsequently be etched. A second layer and third layer may be deposited on the etch first layer, followed by the deposition of a silicon cap. The second and third layer may be etched, exposing edges of the second and third layers. The cap and first layer may be removed and either the second or third layer may be etched, creating a nanoscale pattern. | 04-01-2010 |
Omar George Gebara, Ottawa CA
| Patent application number | Description | Published |
|---|---|---|
| 20100047607 | INSULATING COVER FOR STEAM DISCHARGE TUBES - An insulator for use with a steam discharge tube of the type having two parallel rows of oppositely facing steam discharge apertures is disclosed. Two elongate channel sections having elongate channel edges are positioned transversely between the two rows and extend longitudinally along the tube on opposite sides of the tube. Sealing and spacing means serves to seal in spaced apart relationship the channel sections from the tube on respective opposite sides of the tube and provision is also made for securing said sections to the tube when in their desired location. The resultant insulator in assembled form reduces unwanted condensation production from the steam discharge orifices and also due to no use or the reduced use of polymers, the generation of unwanted off-gases. | 02-25-2010 |