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Gaudiello
John G. Gaudiello, Waterford, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20080206996 | SIDEWALL IMAGE TRANSFER PROCESSES FOR FORMING MULTIPLE LINE-WIDTHS - A method for simultaneously forming multiple line-widths, one of which is less than that achievable employing conventional lithographic techniques. The method includes providing a structure which includes a memory layer and a sidewall image transfer (SIT) layer on top of the memory layer. Then, the SIT layer is patterned resulting in a SIT region. Then, the SIT region is used as a blocking mask during directional etching of the memory layer resulting in a first memory region. Then, a side wall of the SIT region is retreated a retreating distance D in a reference direction resulting in a SIT portion. Said patterning comprises a lithographic process. The retreating distance D is less than a critical dimension CD associated with the lithographic process. The SIT region includes a first dimension W | 08-28-2008 |
| 20090001337 | Phase Change Memory Cell with Vertical Transistor - A memory cell in an integrated circuit is fabricated in part by forming a lower electrode feature, an island, a sacrificial feature, a gate feature, and a phase change feature. The island is formed on the lower electrode feature and has one or more sidewalls. It comprises a lower doped feature, a middle doped feature formed above the lower doped feature, and an upper doped feature formed above the middle doped feature. The sacrificial feature is formed above the island, while the gate feature is formed along each sidewall of the island. The gate feature overlies at least a portion of the middle doped feature of the island and is operative to control an electrical resistance therein. Finally, the phase feature is formed above the island at least in part by replacing at least a portion of the sacrificial feature with a phase change material. The phase change material is operative to switch between lower and higher electrical resistance states in response to an application of an electrical signal. | 01-01-2009 |
John Gerard Gaudiello, Poughkeepsie, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20080258181 | Hybrid Substrates and Methods for Forming Such Hybrid Substrates - Hybrid substrates characterized by semiconductor islands of different crystal orientations and methods of forming such hybrid substrates. The methods involve using a SIMOX process to form an insulating layer. The insulating layer may divide the islands of at least one of the different crystal orientations into mutually aligned device and body regions. The body regions may be electrically floating relative to the device regions. | 10-23-2008 |
John Gerard Gaudiello, Waterford, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20080258222 | Design Structure Incorporating a Hybrid Substrate - Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design in which the design structure includes devices formed in a hybrid substrate characterized by semiconductor islands of different crystal orientations. An insulating layer divides the islands of at least one of the different crystal orientations into mutually aligned device and body regions. The body regions may be electrically floating relative to the device regions. | 10-23-2008 |