Patent application number | Description | Published |
20080208370 | System and method for gap length measurement and control - The present subject matter relates generally to a system and method for controlling functions in a mail sorting system based on gap length measurement and tracking. The system and method includes a plurality of sensors located along one or more mail piece transport paths. The sensors are used to collect data regarding the gap length between each mail piece transported through the system. The gap length data is processed and stored within a controller/processor that uses the gap lengths to control the operation of one or more devices within the mail sorting system. For example, the gap lengths may be used to control the operation of a diverter, a printer or any other electromechanical, hardware or software device. The gap lengths can be used to trigger and/or inhibit the operation of the one or more devices. | 08-28-2008 |
20090159508 | Relational scheme assignment - A method and system are provided for mail item processing within a mail sort environment. In particular, a method and system are provided for allowing different mail sort schemes that share common sort parameters to be referenced to one another in a mail sort environment. There is further provided a method and system to permit mail sort parameter changes as applied to one sort scheme to be readily reflected in any other sort schemes that share the same sort parameters. | 06-25-2009 |
20090218262 | SYSTEM AND METHOD FOR TRACKING A MAIL ITEM THROUGH A DOCUMENT PROCESSING SYSTEM - Processing and tracking of individual mail items processed through a document processing system such as a sorter or inserter utilize a mail item identifier that is unique with respect to each individual mail item. A mail item may have a postal authority approved code representing or containing its associated unique identifier. If not, an identifier is generated and a corresponding postal authority approved code is applied to the mail item. Processing entails associating the unique mail item identifier for each respective mail item with collected metadata for the respective mail item and storing the identifier and associated the metadata. In a sorter example, each mail item is sorted into a postal sort group, and the processing entails identifying the sort group to which each item is sorted and storing the identified sort in association with the unique mail item identifier. | 09-03-2009 |
20090287742 | METHOD AND SYSTEM FOR RUN TIME DIRECTORIES FOR ADDRESS SERVICES ON A MAIL PROCESSING SYSTEM - The present application generally relates to address data maintenance services using a mail processing system. The present application discloses techniques and equipment to update address information and usage of mail processing equipment to print delivery point barcodes that represent the current and accurate address information available for the addressee. The present application also provides a new approach for storing and searching address and name run time directories as part of a mail processing system using address reader technology. | 11-19-2009 |
20090294338 | SYSTEM AND METHOD FOR VALIDATING MAILINGS RECEIVED - The present subject matter relates generally to techniques and/or equipment for validating mail items within a mail processing system. Sort scheme data and mail item identification data are loaded into the mail processing system. The mail item identification data includes a mail owner identification value and a unique mail item identifier. Then, mail item identification data is acquired from each of the mail items processed in the system and validated against the loaded mail item identification data. The method may involve storing mail item validation data. The mail items are sorted in accordance with the loaded sort scheme data. Further, the present subject matter relates generally to building reports based on the information derived from the techniques and/or equipment utilized therein. | 12-03-2009 |
Patent application number | Description | Published |
20080276144 | Method and System for Formal Verification of Partial Good Self Test Fencing Structures - The concept of applying fencing logic to Built-In Self Test (BIST) hardware structures for the purpose of segregating defective circuitry and utilizing the remaining good circuitry is a well known practice in the chip design industry. Described herein is a method for verifying that any particular implementation of partial fencing logic actually provides the desired behavior of blocking down-stream impact of all signals from fenced interfaces, and also ensuring that the partial fencing does not inadvertently preclude any common logic from being fully tested. | 11-06-2008 |
20140149751 | SCALABLE DATA COLLECTION FOR SYSTEM MANAGEMENT - A system with scalable data collection for system management comprises a plurality of local data collectors and a system collector. Each of the local data collectors is coupled with a corresponding subsystem of the system. Each of the local data collectors is configured to periodically collect power management related data from the corresponding subsystem, and to format the collected power management related data for conveyance along any one of a plurality of channels between the local data collector and the system collector. The system collector is coupled with the plurality of local data collectors via the plurality of channels. The system collector selects from the channels between the system collector and each of the local data collectors based, at least in part, on channel states, and retrieves the power management related data collected by each of the local data collectors along a selected channel for the local data collector. | 05-29-2014 |
20140156253 | FUNCTIONAL BUILT-IN SELF TEST FOR A CHIP - According to one embodiment, a self-test system integrated on a chip is provided, the chip including a functional logic module for performing a selected application. The self-test system includes a primary interface a primary interface to the functional logic module, the primary interface configured to interface with a primary device, an input interface protocol generator for generating a pattern to be inserted into the primary interface and a secondary interface to the functional logic module, the secondary interface configured to interface with a secondary device. The system also includes an emulator engine coupled to the secondary interface, the emulator engine for testing a function of the functional logic module based on the inserted patterns, the function being configured to communicate with a secondary device coupled to the secondary interface, wherein the emulator engine tests the function when no secondary device is coupled to the chip. | 06-05-2014 |