| Patent application number | Description | Published |
|---|
| 20080281988 | Apparatus and method for initating a debug halt for a selected architectural state - In a test and debug system wherein a target processing unit in a target processor receives test and debug commands from an external unit, an interface unit included in the target processor monitors the state of the target processing unit. The interface unit receives and stores a test and debug command identifying the test and debug procedure to be performed. Thereafter, the interface unit receives a control signal group indicating the target processing unit state during which the command is to be executed. When the target processor state, indicated by the control signal group, is identified by the interface unit, the stored command is applied to the target processing unit. In this manner, a test and debug procedure can be executed when the target processing unit is in a suitable state. | 11-13-2008 |
| 20080304606 | SYNCHRONIZING A DEVICE THAT HAS BEEN POWER CYCLED TO AN ALREADY OPERATIONAL SYSTEM - A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second remote device while the host device and first remote device are actively operating according to the state diagram. The second remote device waits for a synchronization point sequence. Upon detecting the synchronization point sequence, the second remote device implements a predetermined feature set and synchronizes itself to the state diagram at a common point as the host device and first remote device. | 12-11-2008 |
| 20080307214 | OFFLINE AT START UP OF A POWERED ON DEVICE - A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second remote device while the host device and first remote device are actively operating according to the state diagram. The second remote device determines whether to initialize to a standard protocol or to an advanced protocol. Upon determining to initialize to the advanced protocol, the second remote device then waits for a synchronization point sequence. | 12-11-2008 |
| 20080307279 | SERIAL SCAN CHAIN IN A STAR CONFIGURATION - A method implemented to test a plurality of components coupled in a star configuration, each component having a test access port (TAP) controller. The method comprises performing a capture phase of a scan operation on all of the TAP controllers in the star configuration and sequentially selecting one of the TAP controllers at a time to perform a shift state. When all of the TAP controllers have been sequentially selected to perform the shift phase, the method further comprises selecting all of the TAP controllers to perform an update phase. | 12-11-2008 |
| 20090013226 | BLOCKING THE EFFECTS OF SCAN CHAIN TESTING UPON A CHANGE IN SCAN CHAIN TOPOLOGY - A system comprises a plurality of components, scan chain selection logic coupled to the components, and override selection logic coupled to the scan chain selection logic. The scan chain selection logic selects various of the components to be members of a scan chain under the direction of a host computer. The override selection logic detects a change in the scan chain and, as a result, blocks the entire scan chain from progressing. | 01-08-2009 |
| 20090160488 | Apparatus and method for clock signal synchronization in JTAG testing in systems having modules processing clock signals at different rates - In a test and debug system in which a plurality of modules under test have different operational rates, the system clock and the return clock signals from the modules lose synchronism. An error signal is produced when the clock signal makes a transition to a logic state that is the same logic state of the return clock signal of all of the modules. Apparatus is provided for generating logic signals when all of the return clock signals are in the same logic state. Two logic states are possible for all the return clock signals. A current state is latched until all the return clock signals are in the other state, at which time the second logic signal state is latched. The apparatus can be reset by an external signal. | 06-25-2009 |
| 20090160507 | Apparatus and method for clock signal synchronization in JTAG testing in systems having selectable modules processing data signals at different rates - In a test and debug system in which a plurality of selectable modules under test have different operational rates, a selection unit associated with each module is used to control the application of the RCLK signal from the module to the adder unit, the adder unit providing a composite RCLK signal. Each selection unit has output signals of RCLK_NE and RCLK_PE signals which are applied to an adder unit to form the composite RCLK signal. In response to the SELECT signal, the RCLK_NE and RCLK_PE are synchronized with the module RCLK signal. When the SELECT signal is removed, the RCLK_NE and RCLK_PE signals are continuously applied to the adder unit. it. | 06-25-2009 |
| 20090216521 | Emulation export sequence with distrubuted control - Emulation information including emulation control information and emulation data is exported from a data processor by arranging the emulation information into information blocks, and outputting a sequence of the information blocks from the data processor. Some of the information blocks of the sequence have relative proportions of emulation control information and emulation data that differ from the relative proportions of emulation control information and emulation data in other blocks of the sequence. | 08-27-2009 |
| 20090222695 | SYSTEM AND METHOD FOR SHARING A COMMUNICATIONS LINK BETWEEN MULTIPLE COMMUNICATIONS PROTOCOLS - A system and method for sharing a communications link between multiple protocols is described that comprises a system comprising a communications interface configured to exchange information with other systems using at least one of a plurality of protocols; a protocol select register that stores a value that selects a protocol from among the plurality of protocols to become an active protocol; and a state machine accessible to the communications interface, the state machine used to control the exchange of information through the communications interface according to the active protocol. The active protocol is used by the communications interface to exchange information while the remaining protocols of the plurality of protocols remain inactive. The state machine sequences through a series of states that cause the communications interface to operate according to the active protocol, and that are designated as inert sequences under the remaining protocols. | 09-03-2009 |
| 20100031077 | Alternate Signaling Mechanism Using Clock and Data - Control events may be signaled to a target system having a plurality of components coupled to a scan path by using the clock and data signals of the scan path. While the clock signal is held a high logic level, two or more edge transitions are detected on the data signal. The number of edge transitions on the data signal is counted while the clock signal is held at the high logic state. A control event is determined based on the counted number of edge transitions on the data signal after the clock signal transitions to the low logic state. | 02-04-2010 |
| 20100031089 | Dynamic Broadcast of Configuration Loads Supporting Multiple Transfer Formats - A method for dynamically broadcasting configuration information to controllers connected in a scan topology in a target system is provided in which a selection event followed by the configuration information is received from a signal line at each of the controllers, wherein the plurality of controllers are connected in parallel to the signal line and the configuration information is stored within each controller that matches a selection criteria following the selection event when the selection event initiates a selection sequence. | 02-04-2010 |
| 20100031103 | Selecting a Scan Topology - A controller that shares an interface with several other controllers connected in a scan topology in a target system may be selected by receiving a selection event and a selection sequence containing selection criteria from a signal line at each of the controllers, wherein the criteria for selection is broadcast to the controllers. A controller is placed online when the received selection criteria matches an activation criteria of the controller. | 02-04-2010 |
| 20100031104 | Automatic Scan Format Selection Based on Scan Topology Selection - A method for specifying a signaling protocol to be used by a controller in a group of controllers connected with shared signaling is provided in which the controller is selected based on selection criteria received by the controller and the signaling protocol is specified based on the received selection criteria. | 02-04-2010 |
| 20100223519 | COMPACT JTAG ADAPTER - A system and method for sharing a communications link between multiple protocols is described. A system includes a communications interface configured to exchange information with other systems using at least one of a plurality of protocols; a protocol select register that stores a value that selects a protocol from among the plurality of protocols to become an active protocol; and a state machine accessible to the communications interface, the state machine used to control the exchange of information through the communications interface according to the active protocol. The active protocol is used by the communications interface to exchange information while the remaining protocols of the plurality of protocols remain inactive. The state machine sequences through a series of states that cause the communications interface to operate according to the active protocol, and that are designated as inert sequences under the remaining protocols. | 09-02-2010 |
| 20110113310 | APPARATUS AND METHOD FOR CLOCK SIGNAL SYNCHRONIZATION IN JTAG TESTING IN SYSTEMS HAVING SELECTABLE MODULES PROCESSING DATA SIGNALS AT DIFFERENT RATES - In a test and debug system in which a plurality of selectable modules under test have different operational rates, a selection unit associated with each module is used to control the application of the RCLK signal from the module to the combiner unit, the combiner unit providing a composite RCLK signal. Each selection unit has output signals of RCLK_NE and RCLK_PE signals which are applied to an combiner unit to form the composite RCLK signal. In response to the SELECT signal, the RCLK_NE and RCLK_PE are synchronized with the module RCLK signal. When the SELECT signal is removed, the RCLK_NE and RCLK_PE signals are continuously applied to the combiner unit. | 05-12-2011 |
| 20110113311 | APPARATUS AND METHOD FOR SYNCHRONIZATION WITHIN SYSTEMS HAVING MODULES PROCESSING A CLOCK SIGNAL AT DIFFERENT RATES - In a system in which a plurality of modules have different operational rates and a common clock controlling data delivery to the modules, the rate at which data is delivered to the system can be maximized using a return clock signal to prevent the loss of synchronization of the modules. A clocking error signal may be produced when the clock signal makes a transition to a logic state that may cause loss of synchronization between the modules. | 05-12-2011 |
