| Patent application number | Description | Published |
|---|
| 20080265313 | SEMICONDUCTOR DEVICE HAVING ENHANCED PERFORMANCE AND METHOD - In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a localized region of doping near a portion of a channel region where current exits during operation. | 10-30-2008 |
| 20090014814 | POWER SEMICONDUCTOR DEVICE HAVING IMPROVED PERFORMANCE AND METHOD - In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a counter-doped drain region spaced apart from a channel region. | 01-15-2009 |
| 20090096021 | SEMICONDUCTOR DEVICE HAVING DEEP TRENCH CHARGE COMPENSATION REGIONS AND METHOD - In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a charge compensating trench formed in proximity to active portions of the device. The charge compensating trench includes a trench filled with various layers of semiconductor material including opposite conductivity type layers. | 04-16-2009 |
| 20100059814 | SEMICONDUCTOR DEVICE HAVING VERTICAL CHARGE-COMPENSATED STRUCTURE AND SUB-SURFACE CONNECTING LAYER AND METHOD - In one embodiment, a semiconductor device is formed having vertical localized charge-compensated trenches, trench control regions, and sub-surface doped layers. The vertical localized charge-compensated trenches include at least a pair of opposite conductivity type semiconductor layers. The trench control regions are configured to provide a generally vertical channel region electrically coupling source regions to the sub-surface doped layers. The sub-surface doped layers are further configured to electrically connect the drain-end of the channel to the vertical localized charge compensation trenches. Body regions are configured to isolate the sub-surface doped layers from the surface of the device. | 03-11-2010 |
| 20100059815 | SEMICONDUCTOR TRENCH STRUCTURE HAVING A SEALING PLUG AND METHOD - In one embodiment, a semiconductor device is formed having a trench structure. The trench structure includes a single crystalline semiconductor plug formed along exposed upper surfaces of the trench. In one embodiment, the single crystalline semiconductor plug seals the trench to form a sealed core. | 03-11-2010 |
| 20100148227 | ELECTRONIC DEVICE INCLUDING AN INSULATING LAYER HAVING DIFFERENT THICKNESSES AND A CONDUCTIVE ELECTRODE AND A PROCESS OF FORMING THE SAME - An electronic device includes a transistor, wherein the electronic device can include a semiconductor layer having a primary surface, a channel region, a gate electrode, a source region, a conductive electrode, and an insulating layer lying between the primary surface of the semiconductor layer and the conductive electrode. The insulating layer has a first region and a second region, wherein the first region is thinner than the second region. The channel region, gate electrode, source region, or any combination thereof can lie closer to the first region than the second region. The thinner portion can allow for faster switch of the transistor, and the thicker portion can allow a relatively large voltage difference to be placed across the insulating layer. Alternative shapes for the transitions between the different regions of the insulating layer and exemplary methods to achieve such shapes are also described. | 06-17-2010 |
| 20100148245 | ELECTRONIC DEVICE INCLUDING A TRENCH AND A CONDUCTIVE STRUCTURE THEREIN - An electronic device can include a transistor. In an embodiment, the transistor can include a semiconductor layer having a primary surface and a conductive structure. The conductive structure can include a horizontally-oriented doped re-ion lying adjacent to the primary surface, an underlying doped region spaced apart from the primary surface and the horizontally-oriented doped region, and a vertically-oriented conductive region extending through a majority of the thickness of the semiconductor layer and electrically connecting the doped horizontal region and the underlying doped region. In another embodiment, the transistor can include a gate dielectric layer, wherein the field-effect transistor is designed to have a maximum gate voltage of approximately 20 V, a maximum drain voltage of approximately 30 V, and a figure of merit no greater than approximately 30 mΩ*nC. | 06-17-2010 |
| 20100151646 | PROCESS OF FORMING AN ELECTRONIC DEVICE INCLUDING A TRENCH AND A CONDUCTIVE STRUCTURE THEREIN - A process of forming an electronic device can include providing a workpiece comprising a substrate, including an underlying doped region, and a semiconductor layer overlying the underlying doped region, wherein the semiconductor layer has a primary surface spaced apart from the underlying doped region. The process can also include forming a vertically-oriented conductive region extending from the primary surface to the underlying doped region, and forming a horizontally-oriented doped region adjacent to the primary surface. In a finished form of the electronic device, the horizontally-oriented doped region extends further in a lateral direction toward a region where a source region has been or will be formed, as compared to the vertically-oriented conductive region. The electronic device includes a transistor that includes the underlying doped region, the vertically-oriented conductive region, and the horizontally-oriented doped region. | 06-17-2010 |
| 20100327347 | ELECTRONIC DEVICE INCLUDING A WELL REGION - An electronic device including an integrated circuit can include a buried conductive region and a semiconductor layer overlying the buried conductive region, and a vertical conductive structure extending through the semiconductor layer and electrically connected to the buried conductive region. The integrated circuit can further include a doped structure having an opposite conductivity type as compared to the buried conductive region, lying closer to an opposing surface than to a primary surface of the semiconductor layer, and being electrically connected to the buried conductive region. The integrated circuit can also include a well region that includes a portion of the semiconductor layer, wherein the portion overlies the doped structure and has a lower dopant concentration as compared to the doped structure. In other embodiment, the doped structure can be spaced apart from the buried conductive region. | 12-30-2010 |
| 20100327350 | ELECTRONIC DEVICE INCLUDING AN INTEGRATED CIRCUIT WITH TRANSISTORS COUPLED TO EACH OTHER - An electronic device, including an integrated circuit, can include a buried conductive region and a semiconductor layer overlying the buried conductive region, wherein the semiconductor layer has a primary surface and an opposing surface lying closer to the buried conductive region. The electronic device can also include a first doped region and a second doped region spaced apart from each other, wherein each is within the semiconductor layer and lies closer to primary surface than to the opposing surface. The electronic device can include current-carrying electrodes of transistors. A current-carrying electrode of a particular transistor includes the first doped region and is a source or an emitter and is electrically connected to the buried conductive region. Another current-carrying electrode of a different transistor includes the second doped region and is a drain or a collector and is electrically connected to the buried conductive region. | 12-30-2010 |
| 20110068344 | ELECTRONIC DEVICE INCLUDING A TRENCH AND A CONDUCTIVE STRUCTURE THEREIN - An electronic device can include a transistor. In an embodiment, the transistor can include a semiconductor layer having a primary surface and a conductive structure. The conductive structure can include a horizontally-oriented doped region lying adjacent to the primary surface, an underlying doped region spaced apart from the primary surface and the horizontally-oriented doped region, and a vertically-oriented conductive region extending through a majority of the thickness of the semiconductor layer and electrically connecting the doped horizontal region and the underlying doped region. In another embodiment, the transistor can include a gate dielectric layer, wherein the field-effect transistor is designed to have a maximum gate voltage of approximately 20 V, a maximum drain voltage of approximately 30 V, and a figure of merit no greater than approximately 30 mΩ*nC. | 03-24-2011 |
