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Garrett, Jr.
Billy Garrett, Jr., Mountain View, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090157993 | MECHANISM FOR ENABLING FULL DATA BUS UTILIZATION WITHOUT INCREASING DATA GRANULARITY - A memory is disclosed comprising a first memory portion, a second memory portion, and an interface, wherein the memory portions are electrically isolated from each other and the interface is capable of receiving a row command and a column command in the time it takes to cycle the memory once. By interleaving access requests (comprising row commands and column commands) to the different portions of the memory, and by properly timing these access requests, it is possible to achieve full data bus utilization in the memory without increasing data granularity. | 06-18-2009 |
Billy W. Garrett, Jr., Mountain View, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100134153 | Low Latency Multi-Level Communication Interface - A multiphase receiver to compensate for intersymbol interference in the sampling of an input signal includes a first integrating receiver to integrate and sample data of the input signal on a first phase of a clock and a second integrating receiver to integrate and sample data of the input signal on a second phase of the clock. The multiphase receiver also includes an equalization circuit to adjust integration by the first integrating receiver dependent on a result of integration of data previously received by an integrating receiver distinct from the first integrating receiver, and to adjust integration by the second integrating receiver dependent on a result of integration of data previously received by an integrating receiver distinct from the second integrating receiver. | 06-03-2010 |
| 20110140741 | INTEGRATING RECEIVER WITH PRECHARGE CIRCUITRY - A multiphase receiver to compensate for intersymbol interference in the sampling of an input signal includes a first integrating receiver to integrate and sample data of the input signal on a first phase of a clock and a second integrating receiver to integrate and sample data of the input signal on a second phase of the clock. The multiphase receiver also includes an equalization circuit to adjust integration by the first integrating receiver dependent on a result of integration of data previously received by an integrating receiver distinct from the first integrating receiver, and to adjust integration by the second integrating receiver dependent on a result of integration of data previously received by an integrating receiver distinct from the second integrating receiver. | 06-16-2011 |
Jessie L. Garrett, Jr., Apopka, FL US
Tony Shelby Garrett, Jr., Wilmington, NC US
| Patent application number | Description | Published |
|---|---|---|
| 20120204779 | DOCK SYSTEM INCLUDING COLLAPSIBLE FRAME, AND METHOD FOR ASSEMBLING DOCK SYSTEM INCLUDING COLLAPSIBLE FRAME - A dock system including a collapsible frame, and method for assembling the dock system including collapsible frame are provided. A collapsible dock system includes a collapsible frame. The collapsible frame includes a first beam, a second beam, a cross-member, and a hinged bracket system. The cross-member system secures the first beam to the second beam. The hinged bracket system is selectively coupled to the first beam and the second beam in either a compact transport state in which the first beam is movable relative to the second beam or a fixed installation state in which the first beam is fixed relative to the second beam. | 08-16-2012 |