Patent application number | Description | Published |
20110261550 | USE OF CONDUCTIVE PAINT AS A METHOD OF ELECTROMAGNETIC INTERFERENCE SHIELDING ON SEMICONDUCTOR DEVICES - A conductive paint electromagnetic interference (EMI) shield for an electronic module or device. The conductive paint is composed of metal particles suspended in a fluidic carrier. In one embodiment, the conductive paint is sprayed onto exterior surfaces of an electronic module or device from a spray gun. The sprayed conductive paint is cured to remove the fluidic carrier, leaving a metal film coated to the outside of the module or device. In one embodiment used with electronic packages in array form, grooves are cut into an encapsulation material of a module so that the shield protection includes sidewalls of the package. In another embodiment used with camera modules, masking is used to selectively shield portions of the module. In a further embodiment, the shield is electrically connected to a ground conductor of a circuit of the electronic module. | 10-27-2011 |
20120070145 | METHOD AND SYSTEM FOR SHIELDING SEMICONDUCTOR DEVICES FROM LIGHT - The present disclosure is directed to a camera module that includes at least a semiconducting die, an image-sensing circuit, a lens, a lens aperture, and a coating that adheres to an exterior surface of the camera module. The coating is opaque to light and prevents light from accessing the camera other than through the lens aperture. The opaque coating is applied as a fluid and is cured. In one embodiment, a mask material is selectively applied to exterior surfaces of the semiconducting die, electrical interconnect layers, glass layers, the lens body, or the lens aperture. After applying the opaque coating, the selectively applied mask material is removed. Methods of selectively applying a mask material include applying a conformable and peelably releasable dope-like material, placing an array of joined, selectively shaped rigid masks over an array of assemblies, and applying a conformable mask material that is heat-expandable. | 03-22-2012 |
20140293120 | CONTACT HAVING AN ANGLED PORTION - Described herein are various embodiments of contacts that include different portions angled with respect to one another and methods of manufacturing devices that include such contacts. In some embodiments, a module may include a first portion of a contact that is disposed within a housing and a second portion that is disposed outside of the housing, with the second portion angled with respect to the first portion. Manufacturing such devices may include depositing a conductive material to electrically connect the contact to a contact pad of a substrate. In some embodiments, a deposition process for depositing the conductive material may have a minimum dimension, which defines a minimum dimension of a conductive material once deposited. In some such embodiments, a distance between a terminal end of the contact pin and the contact pad may be greater than the minimum dimension of the deposition process. | 10-02-2014 |
Patent application number | Description | Published |
20110295335 | DEVICE AND IMPLANTATION SYSTEM FOR ELECTRICAL STIMULATION OF BIOLOGICAL SYSTEMS - The present specification discloses devices and methodologies for the treatment of nocturnal GERD. Individuals with nocturnal GERD may be treated by implanting a stimulation device within the patient's lower esophageal sphincter and applying electrical stimulation to the patient's lower esophageal sphincter, in accordance with certain predefined protocols. The presently disclosed devices have a simplified design because they do not require sensing systems capable of sensing when a person is engaged in a wet swallow and have improved energy storage requirements. | 12-01-2011 |
20110295336 | DEVICE AND IMPLANTATION SYSTEM FOR ELECTRICAL STIMULATION OF BIOLOGICAL SYSTEMS - The present specification discloses devices and methodologies for the treatment of diurnal GERD. Individuals with GERD may be treated by implanting a stimulation device within the patient's lower esophageal sphincter and applying electrical stimulation to the patient's lower esophageal sphincter, in accordance with certain predefined protocols. The presently disclosed devices have a simplified design because they do not require sensing systems capable of sensing when a person is engaged in a wet swallow and have improved energy storage requirements. | 12-01-2011 |
20110307027 | DEVICE AND IMPLANTATION SYSTEM FOR ELECTRICAL STIMULATION OF BIOLOGICAL SYSTEMS - The present specification discloses devices and methodologies for the treatment of GERD. Individuals with GERD may be treated by implanting a stimulation device within the patient's lower esophageal sphincter and applying electrical stimulation to the patient's lower esophageal sphincter, in accordance with certain predefined protocols. The presently disclosed devices have a simplified design because they do not require sensing systems capable of sensing when a person is engaged in a wet swallow and have improved energy storage requirements. | 12-15-2011 |
20110307028 | DEVICE AND IMPLANTATION SYSTEM FOR ELECTRICAL STIMULATION OF BIOLOGICAL SYSTEMS - The present specification discloses devices and methodologies for the treatment of transient lower esophageal sphincter relaxations (tLESRs). Individuals with tLESRs may be treated by implanting a stimulation device within the patient's lower esophageal sphincter and applying electrical stimulation to the patient's lower esophageal sphincter, in accordance with certain predefined protocols. The presently disclosed devices have a simplified design because they do not require sensing systems capable of sensing when a person is engaged in a wet swallow and have improved energy storage requirements. | 12-15-2011 |
20130035740 | Device and Implantation System for Electrical Stimulation of Biological Systems - The present specification discloses devices and methodologies for the treatment of GERD. Individuals with GERD may be treated by implanting a stimulation device within the patient's lower esophageal sphincter and applying electrical stimulation to the patient's lower esophageal sphincter, in accordance with certain predefined protocols. The presently disclosed devices have a simplified design because they do not require sensing systems capable of sensing when a person is engaged in a wet swallow, have improved energy storage requirements, enable improved LES function while concurrently delivering additional health benefits, and enable improved LES function post stimulation termination. | 02-07-2013 |
20140094676 | FLEXIBLE, LIGHTWEIGHT PHYSIOLOGICAL MONITOR - Wearable (ambulatory) monitors of the present invention have a segmented design, with at least two and preferably three (or more) mechanically independent, spaced apart sensors (e.g., electrodes or other types of physiological sensors) located in discrete islands, or housing structures that are flexibly connected to one another. Each of the sensors is in operable communication with one or more electronics module(s), also located in one or more of the islands. In some embodiments, an electronics module may be centrally located with respect to two or more peripherally located sensors. | 04-03-2014 |
20160001071 | Device and Implantation System for Electrical Stimulation of Biological Systems - The present specification discloses devices and methodologies for the treatment of GERD. Individuals with GERD may be treated by implanting a stimulation device within the patient's lower esophageal sphincter and applying electrical stimulation to the patient's lower esophageal sphincter, in accordance with certain predefined protocols. The presently disclosed devices have a simplified design because they do not require sensing systems capable of sensing when a person is engaged in a wet swallow, have improved energy storage requirements, enable improved LES function while concurrently delivering additional health benefits, and enable improved LES function post stimulation termination. | 01-07-2016 |
Patent application number | Description | Published |
20140222106 | Device and Implantation System for Electrical Stimulation of Biological Systems - The present specification discloses devices and methodologies for the treatment of GERD. Individuals with GERD may be treated by implanting a stimulation device within the patient's lower esophageal sphincter and applying electrical stimulation to the patient's lower esophageal sphincter, in accordance with certain predefined protocols. The presently disclosed devices have a simplified design because they do not require sensing systems capable of sensing when a person is engaged in a wet swallow and have improved energy storage requirements. | 08-07-2014 |
20140249594 | Device and Implantation System for Electrical Stimulation of Biological Systems - The present specification discloses devices and methodologies for the treatment of transient lower esophageal sphincter relaxations (tLESRs). Individuals with tLESRs may be treated by implanting a stimulation device within the patient's lower esophageal sphincter and applying electrical stimulation to the patient's lower esophageal sphincter, in accordance with certain predefined protocols. The presently disclosed devices have a simplified design because they do not require sensing systems capable of sensing when a person is engaged in a wet swallow and have improved energy storage requirements. | 09-04-2014 |
20150057718 | Device and Implantation System for Electrical Stimulation of Biological Systems - The present specification discloses devices and methodologies for the treatment of transient lower esophageal sphincter relaxations (tLESRs). Individuals with tLESRs may be treated by implanting a stimulation device within the patient's lower esophageal sphincter and applying electrical stimulation to the patient's lower esophageal sphincter, in accordance with certain predefined protocols. The presently disclosed devices have a simplified design because they do not require sensing systems capable of sensing when a person is engaged in a wet swallow and have improved energy storage requirements. | 02-26-2015 |
20150224310 | Device and Implantation System for Electrical Stimulation of Biological Systems - The present specification discloses devices and methodologies for the treatment of transient lower esophageal sphincter relaxations (tLESRs). Individuals with tLESRs may be treated by implanting a stimulation device within the patient's lower esophageal sphincter and applying electrical stimulation to the patient's lower esophageal sphincter, in accordance with certain predefined protocols. The presently disclosed devices have a simplified design because they do not require sensing systems capable of sensing when a person is engaged in a wet swallow and have improved energy storage requirements. | 08-13-2015 |
20160059010 | Device and Implantation System for Electrical Stimulation of Biological Systems - The present specification discloses devices and methodologies for the treatment of transient lower esophageal sphincter relaxations (tLESRs). Individuals with tLESRs may be treated by implanting a stimulation device within the patient's lower esophageal sphincter and applying electrical stimulation to the patient's lower esophageal sphincter, in accordance with certain predefined protocols. The presently disclosed devices have a simplified design because they do not require sensing systems capable of sensing when a person is engaged in a wet swallow and have improved energy storage requirements. | 03-03-2016 |
Patent application number | Description | Published |
20080286978 | ETCHING AND PASSIVATING FOR HIGH ASPECT RATIO FEATURES - An etch method includes etching a masked substrate to form a recess with a first sidewall in the substrate. A thin surface layer of the substrate on the first sidewall is then converted into a passivation layer. The masked substrate is etched again to deepen the recess in the substrate. A surface layer of the substrate on the second sidewall of the recess is then converted into a passivation layer. In one embodiment, upon removal of the passivation layers from both sidewalls, the first and second sidewalls of the high aspect ratio recess are aligned to within 10 Å of each other to provide a high aspect ratio recess having a vertical profile. | 11-20-2008 |
20090017633 | ALTERNATIVE METHOD FOR ADVANCED CMOS LOGIC GATE ETCH APPLICATIONS - Methods for etching, such as for fabricating a CMOS logic gate are provided herein. In some embodiments, a method of etching includes (a) providing a substrate having a first stack and a second stack disposed thereupon, the first stack comprising a high-k dielectric layer, a metal layer formed over the high-k dielectric layer, and a first polysilicon layer formed over the metal layer, the second stack comprising a second polysilicon layer, wherein the first and second stacks are substantially equal in thickness; (b) simultaneously etching a first feature in the first polysilicon layer and a second feature in the second polysilicon layer until the metal layer in the first stack is exposed; (c) simultaneously etching the metal layer and second polysilicon layer to extend the respective first and second features into the first and second stacks; and (d) etching the high-k dielectric layer. | 01-15-2009 |
20090170333 | SHALLOW TRENCH ISOLATION ETCH PROCESS - Methods for fabricating one or more shallow trench isolation (STI) structures are provided herein. In some embodiments, a method for fabricating one or more shallow trench isolation (STI) structures may include providing a substrate having a patterned mask layer disposed thereon to define one or more STI structures. The substrate may be etched using a plasma formed from a process gas mixture to form one or more STI structures on the substrate, wherein the process gas mixture comprises a fluorine-containing gas and either a fluorocarbon-containing gas or a hydrofluorocarbon-containing gas. | 07-02-2009 |
20090221149 | MULTIPLE PORT GAS INJECTION SYSTEM UTILIZED IN A SEMICONDUCTOR PROCESSING SYSTEM - An apparatus having a multiple gas injection port system for providing a high uniform etching rate across the substrate is provided. In one embodiment, the apparatus includes a nozzle in the semiconductor processing apparatus having a hollow cylindrical body having a first outer diameter defining a hollow cylindrical sleeve and a second outer diameter defining a tip, a longitudinal passage formed longitudinally through the body of the hollow cylindrical sleeve and at least partially extending to the tip, and a lateral passage formed in the tip coupled to the longitudinal passage, the lateral passage extending outward from the longitudinal passage having an opening formed on an outer surface of the tip. | 09-03-2009 |
20090221150 | ETCH RATE AND CRITICAL DIMENSION UNIFORMITY BY SELECTION OF FOCUS RING MATERIAL - A method and apparatus are provided for plasma etching a substrate in a processing chamber. A focus ring assembly circumscribes a substrate support, providing uniform processing conditions near the edge of the substrate. The focus ring assembly comprises two rings, a first ring and a second ring, the first ring comprising quartz, and the second ring comprising monocrystalline silicon, silicon carbide, silicon nitride, silicon oxycarbide, silicon oxynitride, or combinations thereof. The second ring is disposed above the first ring near the edge of the substrate, and creates a uniform electric field and gas composition above the edge of the substrate that results in uniform etching across the substrate surface. | 09-03-2009 |
20100210112 | METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE HAVING A LANTHANUM-FAMILY-BASED OXIDE LAYER - Methods for fabricating a semiconductor device having a lanthanum-family-based oxide layer are described. A gate stack having a lanthanum-family-based oxide layer is provided above a substrate. At least a portion of the lanthanum-family-based oxide layer is modified to form a lanthanum-family-based halide portion. The lanthanum-family-based halide portion is removed with a water vapor treatment. | 08-19-2010 |
20120088371 | METHODS FOR ETCHING SUBSTRATES USING PULSED DC VOLTAGE - Methods for etching substrates using a pulsed DC voltage are provided herein. In some embodiments, a method for method for etching a substrate disposed on a substrate support within a process chamber may include providing a process gas to the process chamber; forming a plasma from the process gas; applying a pulsed DC voltage to a first electrode disposed within the process chamber; and etching the substrate while applying the pulsed DC voltage. | 04-12-2012 |
20140199849 | POLYSILICON OVER-ETCH USING HYDROGEN DILUTED PLASMA FOR THREE-DIMENSIONAL GATE ETCH - Methods of polysilicon over-etch using hydrogen diluted plasma for three-dimensional gate etch are described. In an example, a method of forming a three-dimensional gate structure includes performing a main plasma etch on a masked polysilicon layer formed over a semiconductor fin. The method also includes, subsequently, performing a plasma over etch on the masked polysilicon layer based on a plasma generated from gaseous composition including hydrogen gas (H | 07-17-2014 |
Patent application number | Description | Published |
20130087174 | METHODS FOR IN-SITU CHAMBER CLEAN UTILIZED IN AN ETCHING PROCESSING CHAMBER - Embodiments of the invention include methods for in-situ chamber dry cleaning a plasma processing chamber utilized for gate structure fabrication process in semiconductor devices. In one embodiment, a method for in-situ chamber dry clean includes supplying a first cleaning gas including at least a boron containing gas into a processing chamber in absence of a substrate disposed therein, supplying a second cleaning gas including at least a halogen containing gas into the processing chamber in absence of the substrate, and supplying a third cleaning gas including at least an oxygen containing gas into the processing chamber in absence of the substrate. | 04-11-2013 |
20140302678 | INTERNAL PLASMA GRID APPLICATIONS FOR SEMICONDUCTOR FABRICATION - The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid assembly is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers. The plasma grid assembly may include one or more plasma grids having slots of a particular aspect ratio, which allow certain species to pass through from the upper sub-chamber to the lower sub-chamber. In some cases, an electron-ion plasma is generated in the upper sub-chamber. Electrons that make it through the grid to the lower sub-chamber are cooled as they pass through. In some cases, this results in an ion-ion plasma in the lower sub-chamber. The ion-ion plasma may be used to advantage in a variety of etching processes. | 10-09-2014 |
20160086795 | INTERNAL PLASMA GRID APPLICATIONS FOR SEMICONDUCTOR FABRICATION - The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid assembly is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers. The plasma grid assembly may include one or more plasma grids having slots of a particular aspect ratio, which allow certain species to pass through from the upper sub-chamber to the lower sub-chamber. In some cases, an electron-ion plasma is generated in the upper sub-chamber. Electrons that make it through the grid to the lower sub-chamber are cooled as they pass through. In some cases, this results in an ion-ion plasma in the lower sub-chamber. The ion-ion plasma may be used to advantage in a variety of etching processes. | 03-24-2016 |