| Patent application number | Description | Published |
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| 20080267065 | STRUCTURE FOR A MULTI-SCALE NETWORK TRAFFIC GENERATOR - A design structure embodied in a machine readable storage medium for at least one of designing, manufacturing, and testing a design is provided. The design structure includes a network traffic generation system. The system can include a Markov modified Poisson process (MMPP) model, a packet scheduler coupled to the MMP model, a data store of transition windows defined for different defined scales, traffic generation parameter computing logic comprising program code enabled to compute traffic generation parameters for different scales according to respective states identified within different transition windows in the data store for the different scales, and a packet transmitter coupled to the packet scheduler. | 10-30-2008 |
| 20080282028 | DYNAMIC OPTIMIZATION OF DYNAMIC RANDOM ACCESS MEMORY (DRAM) CONTROLLER PAGE POLICY - Embodiments of the present invention address deficiencies of the art in respect to memory management and provide a method, system and computer program product for dynamic optimization of DRAM controller page policy. In one embodiment of the invention, a memory module can include multiple different memories, each including a memory controller coupled to a memory array of memory pages. Each of the memory pages in turn can include a corresponding locality tendency state. A memory bank can be coupled to a sense amplifier and configured to latch selected ones of the memory pages responsive to the memory controller. Finally, the module can include open page policy management logic coupled to the memory controller. The logic can include program code enabled to granularly change open page policy management of the memory bank responsive to identifying a locality tendency state for a page loaded in the memory bank. | 11-13-2008 |
| 20080282029 | STRUCTURE FOR DYNAMIC OPTIMIZATION OF DYNAMIC RANDOM ACCESS MEMORY (DRAM) CONTROLLER PAGE POLICY - A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for dynamic optimization of DRAM controller page policy is provided. The design structure can include a memory module, which can include multiple different memories, each including a memory controller coupled to a memory array of memory pages. Each of the memory pages in turn can include a corresponding locality tendency state. A memory bank can be coupled to a sense amplifier and configured to latch selected ones of the memory pages responsive to the memory controller. Finally, the module can include open page policy management logic coupled to the memory controller. The logic can include program code enabled to granularly change open page policy management of the memory bank responsive to identifying a locality tendency state for a page loaded in the memory bank. | 11-13-2008 |
| 20090083483 | Power Conservation In A RAID Array - Power conservation in a redundant array of inexpensive drives (‘RAID array’) that preserve RAID functionality, the RAID array including RAID subarrays of a same RAID specification, including powering off a drive in at least one of the RAID subarrays; responsive to a write request directed to a particular subarray containing a powered off drive, writing data redundantly to a RAID cache that is independent from the subarray having a powered off drive; powering on the powered-off drive; and flushing the written data from the cache to the particular subarray to which it was originally directed. | 03-26-2009 |
| 20090198886 | Power Conservation in a Composite Array of Data Storage Devices - Operating a composite array of data storage devices, such as hard disk drives, to conserve power includes storing data in block-level stripes with parity on a composite array including a controller and at least three data storage devices. The composite array includes a hot spare distributed across the data storage devices. The method further comprises placing one of the data storage devices in a standby state, operating the rest of the data storage devices in an active state, and controlling logical operations of the controller and the read and write operations of the active data storage devices to substitute for read and write operations on the standby device. For example, the controller can read redundant data on the active drives and compute data identical to the data on the standby drive to substitute for reading the standby drive. Furthermore, the controller can write a modified version of data on the standby drive to a spare block to substitute for writing to the standby drive. | 08-06-2009 |
| 20100037034 | Systems and Methods for Selectively Closing Pages in a Memory - Systems, methods and media for selectively closing pages in a memory in anticipation of a context switch are disclosed. In one embodiment, a table is provided to keep track of open pages for different processes. The table comprises rows corresponding to banks of memory and columns corresponding to cores of a multi-core processing system. When a context switch signal is received, the system unsets a bit in a column corresponding to the core from which the process is to be context-switched out. If no other process is using a page opened by the process the page is closed. | 02-11-2010 |
| 20100191916 | Optimizing A Cache Back Invalidation Policy - A method and a system for utilizing less recently used (LRU) bits and presence bits in selecting cache-lines for eviction from a lower level cache in a processor-memory sub-system. A cache back invalidation (CBI) logic utilizes LRU bits to evict only cache-lines within a LRU group, following a cache miss in the lower level cache. In addition, the CBI logic uses presence bits to (a) indicate whether a cache-line in a lower level cache is also present in a higher level cache and (b) evict only cache-lines in the lower level cache that are not present in a corresponding higher level cache. However, when the lower level cache-line selected for eviction is also present in any higher level cache, CBI logic invalidates the cache-line in the higher level cache. The CBI logic appropriately updates the values of presence bits and LRU bits, following evictions and invalidations. | 07-29-2010 |
| 20100274973 | DATA REORGANIZATION IN NON-UNIFORM CACHE ACCESS CACHES - Embodiments that dynamically reorganize data of cache lines in non-uniform cache access (NUCA) caches are contemplated. Various embodiments comprise a computing device, having one or more processors coupled with one or more NUCA cache elements. The NUCA cache elements may comprise one or more banks of cache memory, wherein ways of the cache are horizontally distributed across multiple banks. To improve access latency of the data by the processors, the computing devices may dynamically propagate cache lines into banks closer to the processors using the cache lines. To accomplish such dynamic reorganization, embodiments may maintain “direction” bits for cache lines. The direction bits may indicate to which processor the data should be moved. Further, embodiments may use the direction bits to make cache line movement decisions. | 10-28-2010 |
| 20100275044 | CACHE ARCHITECTURE WITH DISTRIBUTED STATE BITS - Embodiments that that distribute replacement policy bits and operate the bits in cache memories, such as non-uniform cache access (NUCA) caches, are contemplated. An embodiment may comprise a computing device, such as a computer having multiple processors or multiple cores, which has cache memory elements coupled with the multiple processors or cores. The cache memory device may track usage of cache lines by using a number of bits. For example, a controller of the cache memory may manipulate bits as part of a pseudo least recently used (LRU) system. Some of the bits may be in a centralized area of the cache. Other bits of the pseudo LRU system may be distributed across the cache. Distributing the bits across the cache may enable the system to conserve additional power by turning off the distributed bits. | 10-28-2010 |
| 20100275049 | POWER CONSERVATION IN VERTICALLY-STRIPED NUCA CACHES - Embodiments that dynamically conserve power in non-uniform cache access (NUCA) caches are contemplated. Various embodiments comprise a computing device, having one or more processors coupled with one or more NUCA cache elements. The NUCA cache elements may comprise one or more banks of cache memory, wherein ways of the cache are vertically distributed across multiple banks. To conserve power, the computing devices generally turn off groups of banks, in a sequential manner according to different power states, based on the access latencies of the banks. The computing devices may first turn off groups having the greatest access latencies. The computing devices may conserve additional power by turning of more groups of banks according to different power states, continuing to turn off groups with larger access latencies before turning off groups with the smaller access latencies. | 10-28-2010 |
