Patent application number | Description | Published |
20100232548 | DEMODULATION AND DECODING FOR FREQUENCY MODULATION (FM) RECEIVERS WITH RADIO DATA SYSTEM (RDS) OR RADIO BROADCAST DATA SYSTEM (RBDS) - Demodulation and decoding for frequency modulation (FM) receivers with radio data system (RDS) or radio broadcast data system (RBDS). An example of a method for processing a signal in a receiver includes quantizing a demodulated signal to generate bits in response to receipt of the demodulated signal. The method also includes grouping the bits into one or more blocks. The method further includes computing a syndrome for a block from the one or more blocks. Moreover, the method includes identifying error, corresponding to the syndrome, in the block based on type of demodulation. The type of demodulation includes a coherent demodulation and a differential demodulation. Furthermore, the method includes correcting the error in the block. | 09-16-2010 |
20110111714 | METHOD AND SYSTEM FOR FALSE FREQUENCY LOCK FREE AUTONOMOUS SCAN IN A RECEIVER - Method and system for false lock free autonomous scan in a receiver is disclosed. The method includes identifying a presence of a desired signal to avoid false frequency lock in a Frequency Modulation receiver. The method includes receiving a signal. The method further includes identifying the desired signal, if a first energy is above a first threshold. The method also includes identifying the desired signal, if an Intermediate Frequency count is below a second threshold. The method includes identifying the desired signal, if a second energy of the signal is above a third threshold. The method includes identifying the desired signal, if an absolute difference between a first Received Signal Strength Indication (RSSI) value and a second RSSI value of the signal is below a fourth threshold. The method includes determining a third energy. The method includes identifying the desired signal, if the third energy is below a fifth threshold. | 05-12-2011 |
20120169538 | ENHANCING SEARCH CAPACITY OF GLOBAL NAVIGATION SATELLITE SYSTEM (GNSS) RECEIVERS - Enhancing search capacity of Global Navigation Satellite System (GNSS) receivers. A method for searching satellite signals in a receiver includes performing a plurality of searches sequentially. The method also includes storing a result from each search of the plurality of searches in a consecutive section of a memory. Further, the method includes detecting free sections in the memory. The method also includes concatenating the free sections in the memory to yield a concatenated free section. Moreover, the method includes allocating the concatenated free section for performing an additional search. | 07-05-2012 |
20120230495 | Silence Based Attenuation for Enhanced Idle-Channel FM or Other Receiver Co-Existence with a Coexisting Radio and Circuits, Processes, and Systems - An electronic circuit ( | 09-13-2012 |
20130222181 | ENHANCING SEARCH CAPACITY OF GLOBAL NAVIGATION SATELLITE SYSTEM (GNSS) RECEIVERS - Enhancing search capacity of Global Navigation Satellite System (GNSS) receivers. A method for searching satellite signals in a receiver includes performing a plurality of searches sequentially. The method also includes storing a result from each search of the plurality of searches in a consecutive section of a memory. Further, the method includes detecting free sections in the memory. The method also includes concatenating the free sections in the memory to yield a concatenated free section. Moreover, the method includes allocating the concatenated free section for performing an additional search. | 08-29-2013 |
20130229305 | SYSTEMS AND METHODS FOR DETECTING SATELLITE SIGNALS - A GNSS receiver configured to detect a presence of at least one GNSS satellite signal in a received signal is provided. The GNSS receiver includes a buffer loaded with sample sets corresponding to the received signal and a Doppler derotation block configured to perform a Doppler derotation corresponding to at least one Doppler frequency on a sample set received from the buffer. The GNSS receiver further includes an accumulator block configured to perform a coherent accumulation of a plurality of sample sets upon or subsequent to the Doppler derotation corresponding to a Doppler frequency, and, a first memory configured to store the results of the coherent accumulation. A register array is configured to be loaded with the results stored in the first memory and a correlator engine is configured to generate correlation results by correlating the results in the register array with a plurality of code phases of GNSS satellites. | 09-05-2013 |
20140035784 | ENHANCING SEARCH CAPACITY OF GLOBAL NAVIGATION SATELLITE SYSTEM (GNSS) RECEIVERS - Enhancing search capacity of Global Navigation Satellite System (GNSS) receivers. A method for searching satellite signals in a receiver includes performing a plurality of searches sequentially. The method also includes storing a result from each search of the plurality of searches in a consecutive section of a memory. Further, the method includes detecting free sections in the memory. The method also includes concatenating the free sections in the memory to yield a concatenated free section. Moreover, the method includes allocating the concatenated free section for performing an additional search. | 02-06-2014 |
20150226859 | ENHANCING SEARCH CAPACITY OF GLOBAL NAVIGATION SATELLITE SYSTEM (GNSS) RECEIVERS - Enhancing search capacity of Global Navigation Satellite System (GNSS) receivers. A method for searching satellite signals in a receiver includes performing a plurality of searches sequentially. The method also includes storing a result from each search of the plurality of searches in a consecutive section of a memory. Further, the method includes detecting free sections in the memory. The method also includes concatenating the free sections in the memory to yield a concatenated free section. Moreover, the method includes allocating the concatenated free section for performing an additional search. | 08-13-2015 |
Patent application number | Description | Published |
20080242783 | POLYESTER COMPOSITIONS HAVING IMPROVED HEAT RESISTANCE - A composition of matter comprising a polyester composition derived from: (i) 20 to 80 mole percent of a first diol derived from a disubstituted xylene glycol of the formula (I): | 10-02-2008 |
20080242784 | POLYESTER COMPOSITIONS HAVING IMPROVED HEAT RESISTANCE - A composition of matter comprising a polyester composition derived from: (i) greater than 80 mole percent of a diol derived from a disubstituted xylene glycol of the formula (I): | 10-02-2008 |
20080242829 | METHODS FOR PRODUCING AND PURIFYING 2-HYDROCARBYL-3,3-BIS(4-HYDROXYARYL)PHTHALIMIDINE MONOMERS AND POLYCARBONATES DERIVED THEREFROM - Disclosed herein is a method comprising reacting a phenolphthalein material and a primary hydrocarbyl amine in the presence of an acid catalyst to form a reaction mixture comprising 2-hydrocarbyl-3,3-bis(4-hydroxyaryl)phthalimidine, wherein the phenolphthalein material comprises greater than or equal to 95 weight percent phenolphthalein, based on the total weight of phenolphthalein material; quenching the reaction mixture and treating the quenched reaction mixture to obtain a first solid. The first solid is then triturated with a trituration solvent and washed to obtain a second solid, wherein the second solid comprises greater than or equal to 97 weight percent 2-hydrocarbyl-3,3-bis(4-hydroxyaryl)phthalimidine, based on the total weight of the second solid. The second solid may be polymerized to form a polycarbonate. | 10-02-2008 |
20080242873 | METHODS FOR PRODUCING AND PURIFYING 2-HYDROCARBYL-3,3-BIS(4-HYDROXYARYL)PHTHALIMIDINE MONOMERS AND POLYCARBONATES DERIVED THEREFROM - Disclosed herein is a method comprising reacting a phenolphthalein material and a primary hydrocarbyl amine in the presence of an acid catalyst to form a reaction mixture comprising 2-hydrocarbyl-3,3-bis(4-hydroxyaryl)phthalimidine, wherein the phenolphthalein material comprises greater than or equal to 99 weight percent phenolphthalein, based on the total weight of the phenolphthalein material; quenching the reaction mixture and treating the quenched reaction mixture to obtain a first solid. The first solid is purified by a combination of techniques to produce a solid comprising 2-hydrocarbyl-3,3-bis(4-hydroxyaryl)phthalimidine with sufficient purity to be used as a monomer in the synthesis of clear polymers. | 10-02-2008 |
20120309926 | METHODS FOR PRODUCING AND PURIFYING 2-ARYL-3,3-BIS(4-HYDROXYARYL)PHTHALIMIDINE COMPOUNDS, THE PURIFIED MONOMERS, AND POLYMERS DERIVED THEREFROM - Disclosed is a method for producing a purified 2-aryl-3,3-bis(4-hydroxyaryl)phthalimidine of formula (I) | 12-06-2012 |
20140357830 | METHODS FOR PRODUCING AND PURIFYING 2-ARYL-3,3-BIS(4-HYDROXYARYL)PHTHALIMIDINE COMPOUNDS, THE PURIFIED MONOMERS, AND POLYMERS DERIVED THEREFROM - Disclosed herein is a method for producing a purified 2-aryl-3,3-bis(4-hydroxyaryl) phthalimidine of formula (I) | 12-04-2014 |
Patent application number | Description | Published |
20090158821 | DEVICES, METHODS AND SYSTEMS FOR MEASURING ONE OR MORE CHARACTERISTICS OF A SUSPENSION - A device, method and system for measuring one or more ultrasound parameters of a suspension comprising particles dispersed in a liquid carrier comprising, an immersible devices, comprising, one or more ultrasonic probes; a reflector having staggered reflective; a housing having an opening into the housing to allow the suspension to flow into the space between the probe surface and the reflective surface; an ultrasound wave generator/receiver device; and a signal processing device. | 06-25-2009 |
20110167906 | TORSIONAL SENSOR, METHOD THEREOF, AND SYSTEM FOR MEASUREMENT OF FLUID PARAMETERS - A torsional sensor for sensing at least one parameter of a fluid is disclosed. The torsional sensor includes a torsional portion coupled to a reference portion and including a plurality of projections extending outward and spaced apart from each other. At least a portion of the torsional sensor is mountable for immersion in the fluid and operable to propagate a torsional wave that interacts with the fluid along the at least portion of the torsional sensor so as to affect propagation of the torsional wave in a manner dependent on the at least one parameter of the fluid. | 07-14-2011 |
20120005524 | FAULT TOLERANCE OF MULTI-PROCESSOR SYSTEM WITH DISTRIBUTED CACHE - A semiconductor chip is described having different instances of cache agent logic circuitry for respective cache slices of a distributed cache. The semiconductor chip further includes hash engine logic circuitry comprising: hash logic circuitry to determine, based on an address, that a particular one of the cache slices is to receive a request having the address, and, a first input to receive notice of a failure event for the particular cache slice. The semiconductor chip also includes first circuitry to assign the address to another cache slice of the cache slices in response to the notice. | 01-05-2012 |
20120311360 | Reducing Power Consumption Of Uncore Circuitry Of A Processor - In one embodiment, a multi-core processor includes multiple cores and an uncore, where the uncore includes various logic units including a cache memory, a router, and a power control unit (PCU). The PCU can clock gate at least one of the logic units and the cache memory when the multi-core processor is in a low power state to thus reduce dynamic power consumption. | 12-06-2012 |
20120331310 | Increasing Power Efficiency Of Turbo Mode Operation In A Processor - In one embodiment, a processor has multiple cores to execute threads. The processor further includes a power control logic to enable entry into a turbo mode based on a comparison between a threshold and value of a counter that stores a count of core power and performance combinations that identify turbo mode requests of at least one of the threads. In this way, turbo mode may be entered at a utilization level of the processor that provides for high power efficiency. Other embodiments are described and claimed. | 12-27-2012 |
20130007475 | EFFICIENT FREQUENCY BOOST OPERATION - Systems and methods of operating a computing system may involve identifying a plurality of state values, wherein each state value corresponds to a computing thread associated with a processor. An average value can be determined for the plurality of state values, wherein a determination may be made as to whether to grant a frequency boost request based at least in part on the average value. | 01-03-2013 |
20130042126 | MEMORY LINK POWER MANAGEMENT - Embodiments of the invention describe systems and processes directed towards improving link power-management during memory subsystem idle states. Embodiments of the invention control memory link operations when various components of a memory subsystem enter low power states under certain operating conditions. Embodiments of the invention similarly describe exiting low power states for memory links and various components of a memory subsystem upon detecting certain operating conditions. | 02-14-2013 |
20130042127 | IDLE POWER REDUCTION FOR MEMORY SUBSYSTEMS - Embodiments of the invention describe systems and processes directed towards reducing memory subsystem idle power consumption. Embodiments of the invention enable low power states for various components of a memory subsystem under certain operating conditions, and exiting said low power states under certain operating conditions. | 02-14-2013 |
20130179703 | Increasing Power Efficiency Of Turbo Mode Operation In A Processor - In one embodiment, a processor has multiple cores to execute threads. The processor further includes a power control logic to enable entry into a turbo mode based on a comparison between a threshold and value of a counter that stores a count of core power and performance combinations that identify turbo mode requests of at least one of the threads. In this way, turbo mode may be entered at a utilization level of the processor that provides for high power efficiency. Other embodiments are described and claimed. | 07-11-2013 |
20130179713 | REDUCING POWER CONSUMPTION OF UNCORE CIRCUITRY OF A PROCESSOR - In one embodiment, a multi-core processor includes multiple cores and an uncore, where the uncore includes various logic units including a cache memory, a router, and a power control unit (PCU). The PCU can clock gate at least one of the logic units and the cache memory when the multi-core processor is in a low power state to thus reduce dynamic power consumption. | 07-11-2013 |
20140040543 | Providing State Storage in a Processor for System Management Mode - In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed. | 02-06-2014 |
20140149774 | INCREASING POWER EFFICIENCY OF TURBO MODE OPERATION IN A PROCESSOR - In one embodiment, a processor has multiple cores to execute threads. The processor further includes a power control logic to enable entry into a turbo mode based on a comparison between a threshold and value of a counter that stores a count of core power and performance combinations that identify turbo mode requests of at least one of the threads. In this way, turbo mode may be entered at a utilization level of the processor that provides for high power efficiency. Other embodiments are described and claimed. | 05-29-2014 |
20150039920 | REDUCING POWER CONSUMPTION OF UNCORE CIRCUITRY OF A PROCESSOR - In one embodiment, a multi-core processor includes multiple cores and an uncore, where the uncore includes various logic units including a cache memory, a router, and a power control unit (PCU). The PCU can clock gate at least one of the logic units and the cache memory when the multi-core processor is in a low power state to thus reduce dynamic power consumption. | 02-05-2015 |
Patent application number | Description | Published |
20140177007 | PRINTER CONSUMABLE LOCKING - In one example, a printer consumable is locked to a content provider. A document that includes content restricted by a provider is printed if the printer consumable is installed in the printer. | 06-26-2014 |
20140211232 | CUMULATIVE CONSUMABLE USAGE IN CLOUD-BASED PRINTING SERVICES - In one example, a cloud-based printing service that calculates cumulative usage data of a consumable. | 07-31-2014 |
20140240756 | SENDING PRINTJOBS USING TRIGGER DISTANCES - In one example, a printer address for a network-connected printer, a printer location, and an identifier for a mobile computing device are received. Responsive to receiving a message that is sent to the printer address and that includes a print job, the print job is stored. The identifier is sent to a tracker computing device. A mobile device location is received from the tracker device. Responsive to determining a calculated distance between the mobile device and the printer is less than or equal to a trigger distance, the print job is sent to the printer. | 08-28-2014 |
20140376034 | IDENTIFICATION OF PRINTERS - A system for identifying printers is disclosed herein. An example includes a network and a plurality of printers coupled to the network. The system also includes a device coupled to the network that transmits a current location to the network and a server coupled to the network to produce a map of printers within a proximity of the device based on the current location of the device. The system additionally includes an application associated with the device to selectively produce a sound on at least one of the printers to help identify a location of the printer and to transmit a print job to the identified printer. Other elements and features of the system are disclosed herein, as are examples of a method for identifying networked printers and a non-volatile storage medium. | 12-25-2014 |
Patent application number | Description | Published |
20110248757 | DIGITAL CALIBRATION DEVICE AND METHOD FOR HIGH SPEED DIGITAL SYSTEMS - A digital calibration device and method for a high speed digital system. A digital calibration device coupled to a timing device in a high speed digital system for digitally calibrating the timing device includes a delay estimator, a control logic, and a digitally controlled load unit. In operation, the delay estimator calculates a delay value indicative of a timing delay between a first output and a second output of a timing device of the high speed digital system. Further, the control logic generates a control signal based on the delay value. Furthermore, the digitally controlled load unit applies at least one of a first load to a non-delayed line and a second load to a delayed line of the timing device based on the control signal to calibrate a timing delay between the non-delayed line and the delayed line of the timing device. | 10-13-2011 |
20130034127 | Systems and Methods of Dynamic Spur Mitigation for Wireless Receivers - Example embodiments of the systems and methods of dynamic spur mitigation for wireless receivers disclosed herein comprise one or more of a detection module for detecting the presence of a spur and a determination of its frequency, a complex notch filter chain, and a frequency locked loop which ensures that the input spur is notch filtered even if it drifts after detection. When a spur is detected, the frequency of the tone is determined. The spur is then filtered, for example using a phase rotator and a DC separator. The phase rotation is removed in a subsequent stage. The non-DC component from the DC separator is used to track the spur to compensate for any shifting or drifting in the spur. | 02-07-2013 |
20130147529 | NEAR-INTEGER CHANNEL SPUR MITIGATION IN A PHASE-LOCKED LOOP - A method includes relocating, to a frequency outside a cut-off frequency of a phase-locked loop, a spur frequency component at an input of the phase-locked loop coupled thereto due to an interference of a divided frequency component of an output frequency of the phase-locked loop with a reference clock frequency input thereto through a feedback path thereof when there is a near-integer relationship between the reference clock frequency input and the output frequency. The method also includes filtering the spur frequency component through the phase-locked loop. | 06-13-2013 |
20150117575 | METHOD, SYSTEM AND APPARATUS FOR CARRIER FREQUENCY OFFSET CORRECTION AND CHANNEL ESTIMATION - A receiver is configured to use a first part of a received signal and a second part of the received signal to determine, respectively, a first estimate and a second estimate of the channel. The first and second parts carry information for decoding the received signal in a first protocol and in a second protocol, respectively. A final estimate of the channel is performed from the first and the second estimates. The final estimate is then used for decoding the data in the received signal according to one of the protocols. A carrier frequency offset from a set of symbols occurring prior to preamble symbols is determined and is corrected for decoding the preamble symbols. The corrected preamble symbols are then used for estimating the channel. In one embodiment, the carrier frequency offset is determined for the multiple antenna packet format used in the 802.11n standard. | 04-30-2015 |
Patent application number | Description | Published |
20150089501 | SYSTEMS AND METHODS FOR COLOCATING VIRTUAL MACHINES ON ONE OR MORE PHYSICAL INFRASTRUCTURE - This technology relates to a device and method for determining co-locatability of a plurality of virtual machines on one or more physical infrastructures. The plurality of virtual machines hosts a plurality of workloads. This involves identifying workloads which have high variability from the time series data and determining the workload capacity threshold of the identified workloads. Thereafter, the candidate workloads are selected among the identified workloads to colocate on a virtual machine based on the workload variability. After that, the total capacity required by each candidate workload pair to meet the service requirement is determined based on the workload capacity threshold. Then, an optimal sharing point of each workload of the pair with respect to the other workload of the pair is identified. Further, percentage compatibility of each workload pair is determined and finally, the candidate workloads are colocated based on the optimal sharing point and percentage compatibility. | 03-26-2015 |
20150154498 | METHODS FOR IDENTIFYING SILENT FAILURES IN AN APPLICATION AND DEVICES THEREOF - A method system and computer program product are disclosed for identifying silent failures in an application, comprising of generating a finite state machine (FSM) model of the application based on an input data, extracting state specific invariants relevant to the generated FSM, performing a localized invariant violation check at each state of the generated FSM and upon detection of an invariant violation at any state of the FSM, logging the violation as a silent failure. | 06-04-2015 |
20150227448 | METHODS OF SOFTWARE PERFORMANCE EVALUATION BY RUN-TIME ASSEMBLY CODE EXECUTION AND DEVICES THEREOF - A system and method for evaluating performance of a software application. The present invention includes analyzing by one or more computing devices a plurality of program code lines of the software application stored in one or more computer databases. Further, one or more equivalent program regions within the plurality of program code lines may be identified. One or more markers in the identified one or more equivalent program regions may be inserted and stored in the one or more computer databases. Further, the plurality of program code lines may be compiled and assembled respectively to generate an executable code. The executable code may include a plurality of instructions. Further, performance metrics of the software application may be measured by manipulating the plurality of instructions based on the one or more equivalent program regions identified by the inserted one or more markers and executing the executable code. | 08-13-2015 |