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Ganapathy, CA
Chinnapa K. Ganapathy, San Diego, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090259906 | DATA SUBSTITUTION SCHEME FOR OVERSAMPLED DATA - Low latency and computationally efficient techniques may be employed to account for errors in data such as low bit-width, oversampled data. In some aspects these techniques may be employed to mitigate audio artifacts associated with sigma-delta modulated audio data. In some aspects an error may be detected in a set of encoded data based on an outcome of a channel decoding process. Upon determining that a set of data may contain at least one error, the set of data may be replaced with another set of data that is based on one or more neighboring data sets. For example, in some aspects a set of data including at least one bit in error may be replaced with data that is generated by applying a cross-fading operation to neighboring data sets. In some aspects a given data bit may be flipped as a result of a linear prediction operation that is applied to PCM equivalent data that is associated with the given data bit and its neighboring data bits. In some aspects a set of data including at least one bit in error may be replaced with data that is generated by performing linear interpolation operations on PCM equivalent data that is associated with neighboring data sets. | 10-15-2009 |
Chinnappa K. Ganapathy, San Diego, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090259671 | SYNCHRONIZING TIMING MISMATCH BY DATA INSERTION - The rate at which data is provided by one device and the rate at which that data is processed by another device may differ. For example, a transmitting device may transmit data according to a transmit clock while a receiving device that receives the transmitted data may process the data according to a receive clock. If there is a timing mismatch between the transmit and receive clocks, the receiving device may receive data faster or slower than it processes the data. In such a case, there may be errors relating to the processing of the received data. To address timing mismatches such as this, the receiving device may delete data from or insert data into the received data. In conjunction with these operations, the receiving device may modify the received data at or near the insertion point or the deletion point in a manner that mitigates any adverse effect the insertion or deletion may have on a resulting output signal. | 10-15-2009 |
| 20090259672 | SYNCHRONIZING TIMING MISMATCH BY DATA DELETION - The rate at which data is provided by one device and the rate at which that data is processed by another device may differ. For example, a transmitting device may transmit data according to a transmit clock while a receiving device that receives the transmitted data may process the data according to a receive clock. If there is a timing mismatch between the transmit and receive clocks, the receiving device may receive data faster or slower than it processes the data. In such a case, there may be errors relating to the processing of the received data. To address timing mismatches such as this, the receiving device may delete data from or insert data into the received data. In conjunction with these operations, the receiving device may modify the received data at or near the insertion point or the deletion point in a manner that mitigates any adverse effect the insertion or deletion may have on a resulting output signal. | 10-15-2009 |
| 20090259922 | CHANNEL DECODING-BASED ERROR DETECTION - Low latency and computationally efficient techniques may be employed to account for errors in data such as low bit-width, oversampled data. In some aspects these techniques may be employed to mitigate audio artifacts associated with sigma-delta modulated audio data. In some aspects an error may be detected in a set of encoded data based on an outcome of a channel decoding process. Upon determining that a set of data may contain at least one error, the set of data may be replaced with another set of data that is based on one or more neighboring data sets. For example, in some aspects a set of data including at least one bit in error may be replaced with data that is generated by applying a cross-fading operation to neighboring data sets. In some aspects a given data bit may be flipped as a result of a linear prediction operation that is applied to PCM equivalent data that is associated with the given data bit and its neighboring data bits. In some aspects a set of data including at least one bit in error may be replaced with data that is generated by performing linear interpolation operations on PCM equivalent data that is associated with neighboring data sets. | 10-15-2009 |
| 20100080331 | METHOD AND APPARATUS FOR INTEGRATED CLOCK MISMATCH COMPENSATION AND PACKET LOSS CONCEALMENT - An apparatus and method for processing data are disclosed. The apparatus may include a receiver clock, and a processing system configured to use the receiver clock to receive data from a transmitter, the data being generated with a transmitter clock in the transmitter, wherein the processing system is further configured to estimate a mismatch between the transmitter and receiver clocks, and to determine whether to modify the data based on the estimated mismatch. | 04-01-2010 |
| 20100086073 | SYSTEM AND METHOD TO IMPLEMENT CONCURRENT ORTHOGONAL CHANNELS IN AN ULTRA-WIDE BAND WIRELESS COMMUNICATIONS NETWORK - A system and method for media access control are disclosed. The method comprises providing concurrent orthogonal channels to access media using pulse division multiple access to define pulse positions, wherein the pulse division multiple access includes a time hopping sequence and an offset to distinguish the concurrent orthogonal channels. In addition, the method comprises processing signals associated with at least one of the orthogonal channels. | 04-08-2010 |
| 20100241816 | OPTIMIZED TRANSFER OF PACKETS IN A RESOURCE CONSTRAINED OPERATING ENVIRONMENT - An apparatus includes first and second components, a memory, and an allocator configured to allocate a portion of the memory to the first component, wherein the first component is configured to access the allocated portion of the memory and to send information to the second component to provide the second component with access to the allocated portion of the memory. | 09-23-2010 |
Gopinath Ganapathy, Redwood City, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080221959 | System and architecture for managing distributed design chains - Systems, architectures, and data structures are described which are used to manage distributed design chains, specifically for domains in which data reside in multiple applications and are linked through complex interrelationships. The design chains or design networks integrated by the invention may include multiple companies in multiple sites collaborating to design and develop a new product. The invention is intended to integrate seamlessly and transparently with existing, diverse legacy applications, which include inter-linked data relevant to the design, thereby addressing the needs identified above. | 09-11-2008 |
Hari Ganapathy, San Jose, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080250412 | Cooperative process-wide synchronization - One embodiment relates to a computer-implemented method of concurrently performing a process-wide operation in a multi-threaded process being executed on a computer system so as to result in more efficient performance of the computer system. A plurality of threads of the process concurrently participate in the process-wide operation. Finishing steps of the process-wide operation are performed by a last thread participating in the process-wide operation, regardless of whether the last thread is an initiator thread or a target thread. Other embodiments, aspects, and features are also disclosed. | 10-09-2008 |
Kumar Ganapathy, Mountain View, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090070513 | Method and Apparatus for Distributed Direct Memory Access for Systems on Chip - A distributed direct memory access (DMA) method, apparatus, and system is provided within a system on chip (SOC). DMA controller units are distributed to various functional modules desiring direct memory access. The functional modules interface to a systems bus over which the direct memory access occurs. A global buffer memory, to which the direct memory access is desired, is coupled to the system bus. Bus arbitrators are utilized to arbitrate which functional modules have access to the system bus to perform the direct memory access. Once a functional module is selected by the bus arbitrator to have access to the system bus, it can establish a DMA routine with the global buffer memory. | 03-12-2009 |
Priya Ganapathy, Los Angeles, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110081073 | Methods And Logic For Autonomous Generation Of Ensemble Classifiers, And Systems Incorporating Ensemble Classifiers - In one embodiment, a method for generating an ensemble classifier may include transforming multidimensional training data into a plurality of response planes. Each of the response planes includes a set of confidence scores. The response planes are transformed into a plurality of binary response planes. Each of the binary response planes include a set of binary scores corresponding to one of the confidence scores. Combinations of the binary response planes are transformed into sets of diversity metrics according to a diversity measure. A metric is selected from the sets of diversity metrics. A predicted performance of a child combination of the recognition algorithms corresponding to the combinations is generated. The predicted performance is based at least in part upon the metrics. Parent recognition algorithms are selected from the recognition algorithms based at least in part upon the predicted performance. The ensemble classifier is generated and includes the parent recognition algorithms. | 04-07-2011 |
Visvanathan Ganapathy, Santa Clara, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100242005 | System and method for design, procurement and manufacturing collaboration - A method for designing an electronic component includes receiving a device criteria (e.g., a parametric value, procurement value, etc.) from a designer, querying a database for devices corresponding to the device criteria, querying the database for procurement data and/or engineering data associated with the corresponding devices, presenting the devices to the designer based on the procurement data, and receiving input from the designer identifying one of the presented devices as a selected device. In a particular method, the returned devices are sorted based on one or more procurement values (e.g., manufacturer, price, availability, manufacturer status, etc.), and presented to the designer in a ranked list. Objects representative of the selected devices are then entered into a design file, and the objects are associated with the device's engineering and/or procurement data. In a particular embodiment, the objects are associated with the engineering data by embedding the engineering data in the file object. Optionally, data can be associated with the objects via links to the database. Types of engineering data that can be associated with design file objects include, but are not limited to, device footprint data, device pinout data, device physical dimension data, parametric data, and packaging data. Additionally, connection data and annotation data can be entered into the design file objects by the designer. | 09-23-2010 |