| Patent application number | Description | Published |
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| 20080307240 | POWER MANAGEMENT ELECTRONIC CIRCUITS, SYSTEMS, AND METHODS AND PROCESSES OF MANUFACTURE - An electronic circuit including a power managed circuit ( | 12-11-2008 |
| 20090039952 | System and Method for Auto-Power Gating Synthesis for Active Leakage Reduction - A method includes parsing a design of the integrated circuit to define cells in automatic power gating power domains, automatically creating an automatic power gating power domain netlist from the parsed design of the integrated circuit, and placing and routing the automatic power gating power domain netlist to produce a layout for the integrated circuit. The parsing partitions a high-level power domain of the integrated circuit into one or more automatic power gating power domains. The automatic power gating power domains have substantially zero-cycle power up times, thereby enabling transparent operation. Furthermore, the automatic power gating power domains may be automatically inserted into designs of integrated circuits, thereby relieving integrated circuit designers of the task of inserting power domains and associated hardware and software. | 02-12-2009 |
| 20090046519 | METHOD, DEVICE AND SYSTEM FOR CONFIGURING A STATIC RANDOM ACCESS MEMORY CELL FOR IMPROVED PERFORMANCE - A computer-implemented method of configuring a static random access memory (SRAM) bit cell for operation, an adaptive biasing device and semiconductor wafer testing system. In one embodiment, the method includes: (1) determining a performance characteristic of the SRAM bit cell on a wafer, (2) comparing the performance characteristic to a target and (3) configuring biasing circuitry associated with the SRAM bit cell based on the comparing. | 02-19-2009 |
| 20100103760 | Memory Power Management Systems and Methods - Memory power management systems and methods are provided. One embodiment of the present invention includes a memory power management system. The system comprises a first low dropout (LDO) regulator that provides an active operating voltage that is derived from a first supply voltage to power a memory array during an active mode. The system further comprises a second LDO regulator that provides a minimum memory retention voltage that is derived from a second supply voltage to power the memory array in a standby mode, wherein the second supply voltage also powers at least one peripheral circuit for reading from and/or writing to the memory array. | 04-29-2010 |
| 20100253387 | SYSTEM AND METHOD FOR AUTO-POWER GATING SYNTHESIS FOR ACTIVE LEAKAGE REDUCTION - A method includes parsing a design of the integrated circuit to define cells in automatic power gating power domains, automatically creating an automatic power gating power domain netlist from the parsed design of the integrated circuit, and placing and routing the automatic power gating power domain netlist to produce a layout for the integrated circuit. The parsing partitions a high-level power domain of the integrated circuit into one or more automatic power gating power domains. The automatic power gating power domains have substantially zero-cycle power up times, thereby enabling transparent operation. Furthermore, the automatic power gating power domains may be automatically inserted into designs of integrated circuits, thereby relieving integrated circuit designers of the task of inserting power domains and associated hardware and software. | 10-07-2010 |
| 20100287517 | Statistical Static Timing Analysis in Non-Linear Regions - A method is described for simulating the f-sigma timing path delay of an integrated circuit design when local transistor variations determine the stochastic delay. This is achieved by determining an estimated delay time for a first timing path using non-linear operating point analysis of local variations (NLOPALV). An operating point is calculated for each cell that is included in a timing path in the integrated circuit design. The f-sigma operating point of a cell-arc is a point on the cell-arc delay function (CADF). An f-sigma delay value is determined for each cell using the selected operating point on the CADF of the cell. The determined delay values of the plurality of cells in the timing path may then be combined to predict the estimated delay for the entire timing path. The method may be extended to deal with slew rate, predict hold time statistics, prune paths, and deal with convergent paths. | 11-11-2010 |
| Patent application number | Description | Published |
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| 20090082778 | APPLICATOR, ASSEMBLY, AND METHOD FOR CONNECTING AN INLET CONDUIT TO A HOLLOW ORGAN - The invention provides an applicator for forming a hole in a wall of a hollow organ and for connecting a hemostatic connection assembly to the hollow organ, wherein, when the hole is formed in the wall of the hollow organ, a first fluid seal exists between the hemostatic connection assembly and the wall of the hollow organ and a second fluid seal exists between the hemostatic connection assembly and the applicator, thereby minimizing fluid loss from the hollow organ. The invention further provides a hemostatic connection assembly for connecting an inlet conduit to a hollow organ, the hemostatic connection assembly comprising a organ wall connection portion, a cuff portion, an extension portion, and a seal ring portion, wherein, during the process of connecting the inlet conduit to the hollow organ, a first fluid seal exists between the organ wall connection portion and the wall of the hollow organ, and a second fluid seal exists between the hemostatic connection assembly and the inlet conduit, thereby minimizing fluid loss from the hollow organ. A method is also disclosed in which the applicator and hemostatic connection assemblies of the invention are used to connect an inlet conduit to a hollow organ. | 03-26-2009 |
| 20100010500 | Apparatus and method for connecting a conduit to a hollow organ - An apparatus and method for connecting a first conduit to the heart without the need for cardiopulmonary bypass. The first conduit may then be attached to a second conduit that has a prosthetic device interposed. The second conduit may then be connected to the aorta. The prosthetic device may be a prosthetic valve or a pump, for example. The apparatus of the present invention includes an implantable connector with first conduit component, a retractor expansion component, a coring component, and a pushing component. The retractor expansion component is slide-ably coupled to the coring component. The retractor expansion component serves to seat against and separate the inside apical wall of the left ventricle so that the coring component may cut cleanly through the myocardium to form a tissue plug without leaving any hanging attachments to the inside walls. By remaining seated against the inside wall, the retractor expansion component follows the tissue plug into the coring component. The surgeon applies force and rotary motion to the pushing component sufficient to cut the tissue plug and implant the prosthetic component. | 01-14-2010 |
| 20110118763 | METHOD AND APPARATUS FOR EFFECTING AN AORTIC VALVE BYPASS, INCLUDING THE PROVISION AND USE OF A T-STENT FOR EFFECTING A DISTAL ANASTOMOSIS FOR THE SAME - A connector for joining a first hollow structure to the side wall of a second hollow structure, the connector comprising:
| 05-19-2011 |
