| Patent application number | Description | Published |
|---|
| 20100175750 | ENHANCED EFFICIENCY SOLAR CELLS AND METHOD OF MANUFACTURE - Enhanced efficiency solar cells and methods of manufacture of such cells are described herein. In an illustrative example, the solar cell includes at least one or more collector lens bars each of which extend on sides of front contacts and positioned over a respective active area of one or more active areas in such as position as to guide light onto the one or more active areas. A protective layer covers the at least one or more collector lens bars. | 07-15-2010 |
| 20100314768 | INTERCONNECT STRUCTURE FABRICATED WITHOUT DRY PLASMA ETCH PROCESSING - An interconnect structure within a microelectronic structure and a method for fabricating the interconnect structure within the microelectronic structure use a developable bottom anti-reflective coating layer and at least one imageable inter-level dielectric layer located thereupon over a substrate that includes a base dielectric layer and a first conductor layer located and formed embedded within the base dielectric layer. Incident to use of the developable bottom anti-reflective coating layer and the at least one imageable inter-level dielectric layer, an aperture, such as but not limited to a dual damascene aperture, may be formed through the at least one imageable inter-level dielectric layer and the developable anti-reflective coating layer to expose a capping layer located and formed upon the first conductor layer, absent use of a dry plasma etch method when forming the interconnect structure within the microelectronic structure. | 12-16-2010 |
| 20110012249 | IC CHIP PACKAGE HAVING IC CHIP WITH OVERHANG AND/OR BGA BLOCKING UNDERFILL MATERIAL FLOW AND RELATED METHODS - An IC chip package, in one embodiment, may include an IC chip including an upper surface including an overhang extending beyond a sidewall of the IC chip, and underfill material about the sidewall and under the overhang. The overhang prevents underfill material from extending over an upper surface of the IC chip. In another embodiment, a ball grid array (BGA) is first mounted to landing pads on a lower of two joined IC chip packages. Since the BGA is formed on the lower IC chip package first, the BGA acts as a dam for the underfill material thereon. The underfill material extends about the respective IC chip and surrounds a bottom portion of a plurality of solder elements of the BGA and at least a portion of respective landing pads thereof. | 01-20-2011 |
| 20110068424 | THICK BOND PAD FOR CHIP WITH CAVITY PACKAGE - Disclosed herein an image sensor chip, including a substrate having at least one via extending through at least one inter layer dielectric (ILD); a first conductive layer over the ILD, wherein the first conductive layer has a first thickness; a second conductive layer over the first conductive layer, wherein the second conductive layer has a second thickness of less than the first thickness; a polymer layer over the second conductive layer, the polymer layer including a cavity; a plurality of cavity components in the cavity; and an optically transparent layer contacting the polymer layer and covering the cavity. | 03-24-2011 |
| 20110068436 | METHODS AND STRUCTURES FOR ENHANCING PERIMETER-TO-SURFACE AREA HOMOGENEITY - Methods and structures for enhancing the homogeneity in a ratio of perimeter to surface area among heterogeneous features in different substrate regions. At least one shape on the substrate includes an added edge effective to reduce a difference in the perimeter-to-surface area ratio between the features in a first substrate region and features in a second substrate region. The improved homogeneity in the perimeter-to-surface area ratio reduces variations in a thickness of a conformal layer deposited across the features in the first and second substrate regions. | 03-24-2011 |
