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Galera
Manolito Galera, Singapore PH
| Patent application number | Description | Published |
|---|---|---|
| 20100127365 | LEADFRAME-BASED CHIP SCALE SEMICONDUCTOR PACKAGES - Chip scale semiconductor packages and methods for making and using the same are described. The chip scale semiconductor packages comprise a leadframe supporting a die that contains a discrete device. The chip scale semiconductor device also contains and an interconnect structure that also serves as a land for the package. The leadframe contains a topset feature adjacent a die attach pad supporting the die, a configuration which provides a connection to the interconnect structure as well as the backside of the die. This leadframe configuration provides a maximum die size to be used in the chip scale semiconductor packages while allowing them to be used in low power and ultra-portable electronic devices. Other embodiments are described. | 05-27-2010 |
| 20100127380 | LEADFRAME FREE LEADLESS ARRAY SEMICONDUCTOR PACKAGES - Leadframe-free semiconductor packages and methods for making and using the same are described. The semiconductor packages contain an interconnect structure comprising an array of land pads. The interconnect structure is formed from and routed using a printable or wirebondable conductive material and is not formed using any etching procedure. A solderable mask covers the interconnect structure except for the land pads. A die containing an integrated circuit device is connected to the interconnect structure by either a wirebonding process or by a flipchip process. The land pad arrays can contain a solder connector, such as a solder ball or bump, that can be used to connect the semiconductor package to a printed circuit board. Other embodiments are described. | 05-27-2010 |
| 20110121453 | SEMICONDUCTOR SYSTEM-IN-PACKAGE AND METHOD FOR MAKING THE SAME - Semiconductor devices that contain a system in package and methods for making such packages are described. The semiconductor device with a system in package (SIP) contains a first IC die, passive components, and discrete devices that are contained in a lower level of the package. The SIP also contains a second IC die that is vertically separated from the first IC die by an array of metal interposers, thereby isolating the components of the first IC die from the components of the second IC die. Such a configuration provides more functionality within a single semiconductor package while also reducing or eliminating local heating in the package. Other embodiments are also described. | 05-26-2011 |
Manolito Fabres Galera, Singapore SG
| Patent application number | Description | Published |
|---|---|---|
| 20100140773 | STACKED CHIP, MICRO-LAYERED LEAD FRAME SEMICONDUCTOR PACKAGE - Semiconductor packages that contain stacked chips on a micro-layered lead frame and methods for making such semiconductor packages are described. The semiconductor packages contain a full array of land pads that has been formed from a lead frame. The packages comprise multiple chips that are stacked vertically and separated by routing leads which are connected to the land pad array. The routing leads can be etched from a metal cladding layer that is provided between each set of stacked chips. Each chip and its routing leads can be encapsulated before the next chip is provided in the package. The semiconductor packages therefore have a high input/output capability with a small package footprint, a flexible routing capability, and a small thickness for multiple chips that are stacked in the package. Other embodiments are also described. | 06-10-2010 |
| 20100244211 | MULTICHIP DISCRETE PACKAGE - A multichip discrete package with a leadframe having a plurality of leads and a first die attach pad (DAP), the first DAP having side portions that extend above the first DAP, a first discrete die bonded to the first DAP, at least a first wirebond which forms an electrical connections between the first discrete die and a first selected one of the plurality of leads, a metal plate attached to tops of the side portions forming a second DAP, a second discrete die bonded to the second DAP, at least a second wirebond which forms an electrical connections between the second discrete die and a second selected one of the leads; and encapsulating material formed around the first and second die and the first and second DAPs. | 09-30-2010 |
| 20110163428 | SEMICONDUCTOR PACKAGES WITH EMBEDDED HEAT SINK - Semiconductor packages and methods for making and using the same are described. The semiconductor packages contain a leadframe having an array of holes with a layout corresponding to the land pad array of the package, wherein the holes contain a thermally-conductive dielectric material with a via therein containing an electrically conductive material. The electrically conductive materials can extend past the bottom of the leadframe to form the land pad array of the packages. With such a configuration, the leadframe can act as an embedded heat sink in the package and there is no need to mount an additional heat sink to the package for thermal dissipation, allowing a thinner package to be manufactured. With such a configuration, the semiconductor packages have a full land pad array, providing a smaller footprint and a higher I/O capacity. Other embodiments are also described. | 07-07-2011 |
Manolito Fabres Galera, Singapore PH
| Patent application number | Description | Published |
|---|---|---|
| 20110193206 | STACKABLE SEMICONDUCTOR PACKAGE WITH EMBEDDED DIE IN PRE-MOLDED CARRIER FRAME - Semiconductor packages that contain multiple stacked chips that are embedded in a pre-molded carrier frame and methods for making such semiconductor packages are described. The semiconductor packages contain a full land pad array and multiple chips that are stacked vertically. The land pad array contains inner terminals that are formed by first stud bumps that are located on a lower die. The land pad array also contains middle terminals that are formed by first conductive vias in a first molding layer embedding the first die. The first conductive vias are connected to second stud bumps that are located on a second die that is embedded in a second molding layer. The second molding layer contains second conductive vias that are connected to a carrier frame, the bottom of which forms the outer terminals of the land pad array. The semiconductor packages therefore have a high input/output capability with a small package footprint, and a flexible routing capability that are especially useful for portable and ultra-portable electronic apparatus. Other embodiments are also described. | 08-11-2011 |
Monolito Galera, Singapore SG
| Patent application number | Description | Published |
|---|---|---|
| 20100181660 | Multi-Chip Semiconductor Package - Semiconductor packages that contain multiple stacked chips and methods for making such semiconductor packages are described. The semiconductor packages contain a full land pad array and multiple chips that are stacked vertically. Some of the chips are separated by routing leads which are connected to the land pad array. The chips can be directly connected to an inner part of the land pad array and a second and third chip are respectively connected to the middle and outer part of the land pad array through the routing leads that are connected to solder balls. The semiconductor packages therefore have a high input/output capability with a small package footprint, and a flexible routing capability. Other embodiments are also described. | 07-22-2010 |
Richard Galera, Nashua, NH US
| Patent application number | Description | Published |
|---|---|---|
| 20110298579 | DYNAMICALLY ADAPTABLE SAFETY ZONES - Systems and methods are provided for defining a safety zone in an industrial automation environment. The method includes monitoring an object that approaches an operating zone where equipment is controlled within the operating zone. This includes determining the speed or direction that the object approaches the operating zone. The method includes dynamically adjusting a safety region in view of the determined speed or direction of the object and enabling or disabling the equipment within the operating zone based in part on the object entering the safety region. | 12-08-2011 |