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Gala, US
Alan Gala, Mount Kisco, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20110208894 | PHYSICAL ALIASING FOR THREAD LEVEL SPECULATION WITH A SPECULATION BLIND CACHE - A multiprocessor system includes nodes. Each node includes a data path that includes a core, a TLB, and a first level cache implementing disambiguation. The system also includes at least one second level cache and a main memory. For thread memory access requests, the core uses an address associated with an instruction format of the core. The first level cache uses an address format related to the size of the main memory plus an offset corresponding to hardware thread meta data. The second level cache uses a physical main memory address plus software thread meta data to store the memory access request. The second level cache accesses the main memory using the physical address with neither the offset nor the thread meta data after resolving speculation. In short, this system includes mapping of a virtual address to a different physical addresses for value disambiguation for different threads. | 08-25-2011 |
Dinesh Gala, East Brunswick, NJ US
| Patent application number | Description | Published |
|---|---|---|
| 20100249411 | Stereoselective Alkylation of Chiral 2-Methly-4 Protected Piperazines - In an illustrative embodiment, the present invention describes the synthesis of the following compound and similar compounds, in high stereochemical purity by a novel stereoselective alkylation process: | 09-30-2010 |
Heman Gala, Schaumburg, IL US
| Patent application number | Description | Published |
|---|---|---|
| 20100060651 | Pipelined image processing engine - The present invention related to processing image frames through a pipeline of effects by breaking the image frames into multiple blocks of image data. The example method includes generating a plurality of blocks from each frame, processing each block through a pipeline of effects in a predefined consecutive order, and aggregating the processed blocks to produce an output frame by combining the primary pixels from each processed block. The pipeline of effects may be distributed over a plurality of processing nodes, and each effect may process a block, provided as input to the node. Each processing node may independently process a block using an effect. | 03-11-2010 |
Hemant B. Gala, Arlington Heights, IL US
| Patent application number | Description | Published |
|---|---|---|
| 20100163454 | HYDROCRACKING PROCESSES YIELDING A HYDROISOMERIZED PRODUCT FOR LUBE BASE STOCKS - Methods are disclosed for hydrocracking processes that convert a significant portion of a heavy hydrocarbon feedstock such as vacuum gas oil (VGO) to lower molecular weight, lower boiling hydrocarbons. In addition to molecular weight reduction, the processes also substantially reduce the pour point of a recovered higher boiling fraction or unconverted oil, all or a portion of which may be used as a lube base stock, optionally after one or more further treatment steps such as hydrofinishing. The ability to reduce the pour point, through hydroisomerization, of the higher boiling fraction greatly improves the quality of this fraction, or unconverted oil, for use in lube base stock preparation. Advantageously, separate, conventional hydroisomerization and/or dewaxing steps, often requiring a noble metal catalyst, may be avoided in particular embodiments disclosed herein. | 07-01-2010 |
Kajal Gala, New York, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20080209770 | SHOE FOR PROFESSIONAL TRUCKERS | 09-04-2008 |
Kumar Gala, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20080222389 | INTERPROCESSOR MESSAGE TRANSMISSION VIA COHERENCY-BASED INTERCONNECT - A method includes communicating a first message between processors of a multiprocessor system via a coherency interconnect, whereby the first message includes coherency information. The method further includes communicating a second message between processors of the multiprocessor system via the coherency interconnect, whereby the second message includes interprocessor message information. A system includes a coherency interconnect and a processor. The processor includes an interface configured to receive messages from the coherency interconnect, each message including one of coherency information or interprocessor message information. The processor further includes a coherency management module configured to process coherency information obtained from at least one of the messages and an interrupt controller configured to generate an interrupt based on interprocessor message information obtained from at least one of the messages. | 09-11-2008 |
| 20080235713 | Distributed Processing System and Method - A method is disclosed that receives a function call at an application program interface. The method selects a first processor of a plurality of processors to execute the function call. The method further executes a first transmit function associated with a bus coupled to the first processor. The first transmit function includes a function parameter associated with the function call. | 09-25-2008 |
| 20080239954 | METHOD AND SYSTEM FOR COMMUNICATION BETWEEN NODES - A method of communicating with a network interface includes providing a packet to the network interface, where the packet includes an address field indicating a destination of the packet. The network interface analyzes the address field, and determines if it reflects an address associated with the network interface. If not, the network interface provides the packet to a network. If the network interface determines the address field reflects an address associated with the interface, it provides information in the packet to an application executing at the network interface. Accordingly, information targeted to an application can be communicated by associating an address, such as a network address, with the network interface, allowing for communication of the information without extensive processing of each packet at the interface. | 10-02-2008 |
Kumar K. Gala US
| Patent application number | Description | Published |
|---|---|---|
| 20110208949 | HARDWARE THREAD DISABLE WITH STATUS INDICATING SAFE SHARED RESOURCE CONDITION - A technique for indicating a safe shared resource condition with respect to a disabled thread provides a mechanism for providing a fast indication to other hardware threads that a temporarily disabled thread can no longer impact shared resources, such as shared special-purpose registers and translation look-aside buffers within the processor core. Signals from pipelines within the core indicates whether any of the instructions pending in the pipeline impact the shared resources and if not, then the thread disable status is presented to the other threads via a state change in a thread status register. Upon receiving an indication that a particular hardware thread is to be disabled, control logic halts the dispatch of instructions for the particular hardware thread, and then waits until any indication that a shared resource is impacted by an instruction has cleared. Then the control logic updates the thread status to indicate the thread is disabled. | 08-25-2011 |
Michael Joseph Gala, Apex, NC US
| Patent application number | Description | Published |
|---|---|---|
| 20100009825 | Compliant Service Transfer Module for Robotic Tool Changer - A compliant service transfer module, which transfers services such as electricity, data, pneumatic fluid, etc., between a robotic arm and an attached tool, aligns service transfer points as the two units of the module mate, when the units are misaligned. A floating structure disposed in the first unit is operative to move laterally within a chamber in the housing of the first unit, to align service transfer points with the corresponding service transfer points of a second unit, when the two units are mated together but are not fully aligned. The floating structure protrudes from the first housing, and in the case of misalignment, contacts an angled inner wall of a chamber in the housing of the second unit, which moves the floating structure laterally to align the service transfer points. The floating structure returns to a default, centered position when the two units are not mated together. | 01-14-2010 |
Mitesh Gala, Los Alamitos, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100312606 | Systems and Methods for Personnel Monitoring and Management - The systems and methods for providing an integrated means for monitoring, managing and auditing employees performance at a workplace or job site, such as monitoring the time worked by the employees, ensuring employee compliance with applicable laws and regulations, and coordinating and assigning duties to be performed by the employees. Each employee may be provided with a mobile wireless device in communication with the system to provide alerts of potential or actual violations, notifications of any change in duties or position, and notification of time clock status (i.e., time to take a break, time to clock in, etc.). | 12-09-2010 |
Mrinal Gala, Houston, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20080200565 | Surfactant-only microemulsions for cleaning system design and product delivery - Surfactant systems are provided that, upon contact with an oil, can produce a Windsor Type III middle phase microemulsion at a total surfactant concentration of 1.5% to 1.0% or less based on the weight of water in the surfactant system, without the need for a cosolvent or linking molecule. The microemulsions can have a separation time less than about 2 hours and even less than about 15 minutes. | 08-21-2008 |
Murali Gala, San Jose, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100332924 | AT-SPEED SCAN TESTING OF MEMORY ARRAYS - An integrated circuit configured for at-speed scan testing of memory arrays. The integrated circuit includes a scan chain having a plurality of serially coupled scan elements, wherein a subset of the plurality of scan elements are coupled to provide signals to a memory array. Each scan element of the subset of the plurality of scan elements includes a flip flop having a data input, and a data output coupled to a corresponding input of the memory array, and selection circuitry configured to, in an operational mode, couple a data path to the data input, and further configured to, in a scan mode, couple to the data input one of a scan input, the data output, and a complement of the data output. The scan elements of the subset support at-speed testing of a memory array coupled thereto. | 12-30-2010 |
Murali Mohan Reddy Gala, San Jose, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100235683 | TESTING MULTI-CORE PROCESSORS - Methods and apparatuses are disclosed for testing multicore processors. In some embodiments, the tested multicore processor may include at least a first core and a second core, a data input coupled to a first scan chain in the first core and a second scan chain in the second core, and a multiplexer including at least a first input and a second input, the first input coupled with a data output of the first scan chain and the second input coupled with a data output of the second scan chain, the multiplexer further including an output that couples to one or more pins on a package of the processor, the multiplexer further including a select signal that couples to the one or more pins on the package of the processor, and wherein the data input couples to the one or more pins on the package of the processor. | 09-16-2010 |