| Patent application number | Description | Published |
|---|
| 20100005199 | DIRECT MEMORY ACCESS (DMA) DATA TRANSFERS WITH REDUCED OVERHEAD - A digital processing system, in which a single interrupt to a processor is used in transferring multiple messages in the form of corresponding packets. In an embodiment, a processor continues to write messages to a transmit first-in-first-out (FIFO) along with a length of the message in a header of a packet. A direct memory access (DMA) controller compares the length indicated in the header with the unread data in the transmit FIFO to determine whether a complete message is stored in the transmit FIFO. DMA controller starts transmission of only complete messages thereafter. A single interrupt is generated when no complete message is determined to be present in the transmit FIFO. Similar features may be used to reduce interrupts to the processors, when transmitting data to the processor. | 01-07-2010 |
| 20100034248 | HARDWARE INITIATED THROUGHPUT (HITM) MEASUREMENT INSIDE AN OCP SYSTEM USING OCP SIDE BAND SIGNALS - A method, system, and apparatus to hardware initiated throughput (HITM) measurement inside an OCP system using OCP side band signals are disclosed. In one embodiment, a system of an integrated circuit includes a signal line located in the integrated circuit to communicate an electrical signal, a receiver circuit located in the integrated circuit coupled to the signal line, a transmitter module located in the integrated circuit to communicate a data stream to the receiver circuit through the signal line, and a throughput monitor circuit coupled to the signal line to measure a throughput value during a communication period of the data stream from the transmitter module. The system may include a processor module located in the integrated circuit configured to interrupt an operation of the transmitter module and a receiver module if the throughput monitor circuit generates the interrupt signal. | 02-11-2010 |
| 20100036986 | SYSTEM FOR DEBUGGING THROUGHPUT DEFICIENCY IN AN ARCHITECTURE USING ON-CHIP THROUGHPUT COMPUTATIONS - A method, system, and apparatus for debugging throughput deficiency in an architecture using on-chip throughput computations are disclosed. In one embodiment, a system includes a subsystem module of the integrated circuit (e.g., may be a field-programmable gate array), a other subsystem module associated with the subsystem module to execute a specified function of the integrated circuit, an interconnect module comprising a transmission line to associate the subsystem module to the other subsystem module, and a throughput monitor circuit (e.g., may continuously determine the throughput value) located in the integrated circuit and coupled with the interconnect module to measure a throughput value as a specified number of data bits per a specified period of time. The system may include, an interrupt generation circuit located in the integrated circuit and coupled with the throughput monitor circuit to determine whether the throughput value is less than a specified throughput value. | 02-11-2010 |
