Patent application number | Description | Published |
20090097308 | MULTIVALUE MEMORY STORAGE WITH TWO GATING TRANSISTORS - Digital memory devices and systems, as well as methods of operating digital memory devices, that include a multivalue memory cell with a first and a second gating transistor arranged in parallel, having a first and a second node, respectively, coupled to a storage element, and sensing circuitry coupled to a third and a fourth node of the first and second gating transistors, respectively, to sense a stored voltage of the memory cell. In embodiments, the first and second gating transistors are configured to activate at different threshold voltage levels. | 04-16-2009 |
20090103386 | SELECTIVELY-POWERED MEMORIES - Embodiments provide methods, apparatuses and systems including a plurality of memory cells configured to store bit values while being powered at a power-saving voltage lower than a normal-operation voltage during operation of a host apparatus, and power circuitry coupled to the plurality of memory cells. The power circuitry is configured to selectively power a first subset of the plurality of memory cells at the normal-operation voltage during operation of the host apparatus while concurrently powering a second subset of the plurality of memory cells at the power-saving voltage. The first and second subsets being different subsets of the memory cells. | 04-23-2009 |
20090106505 | DIGITAL MEMORY WITH FINE GRAIN WRITE OPERATION - Methods, systems, and apparatus for operating digital memory including determining, by a controller, a bit to be written to the digital memory and writing, by the controller, the bit. The bit may be part of a data word comprising a plurality of bits and both the determining and the writing may be performed at a granularity level finer than a data word. In embodiments, the bit to be written may be determined by error correction. | 04-23-2009 |
20090106508 | DIGITAL MEMORY WITH CONTROLLABLE INPUT/OUTPUT TERMINALS - Methods and apparatus for controlling an input/output (I/O) driver of an I/O terminal based at least in part on the values being provided to the I/O terminal is disclosed. In various embodiments, a detector is employed. The detector shuts off power to the I/O driver if the digital value being presented is the same as a previously presented digital value. | 04-23-2009 |
20090122627 | MEMORY WITH PROGRAMMABLE STRIDES - Embodiments of the present disclosure provide methods, apparatuses and systems including a storage configured to store and output multiple address strides of varying sizes to enable access and precharge circuitry to access and precharge a first and a second group of memory cells based at least in part on the multiple address strides during operation of the host apparatus/system, the first and second group of memory cells being different groups of memory cells. | 05-14-2009 |
20090237997 | RANDOM ACCESS MEMORY WITH CMOS-COMPATIBLE NONVOLATILE STORAGE ELEMENT - Embodiments provide systems, methods, and apparatuses with a plurality of row lines and column lines arranged in a matrix, and at least one memory cell having an access transistor and a CMOS-compatible non-volatile storage element coupled to the access transistor in series. The CMOS-compatible non-volatile storage element includes a node and is configured to hold a charge corresponding to a n-bit binary value where n is an integer greater than 1. The access transistor has a word line gate coupled to a row line, a first node coupled to a column line, a second node coupled to a storage node, with the storage node connected to said node of the CMOS-compatible non-volatile storage element. Access circuitry coupled to the memory cell is configured to activate the memory cell and sense a resulting current corresponding to the n-bit binary value. | 09-24-2009 |
20100006138 | SEMICONDUCTOR DEVICES WITH GRADED DOPANT REGIONS - Most semiconductor devices manufactured today, have uniform dopant concentration, either in the lateral or vertical device active (and isolation) regions. By grading the dopant concentration, the performance in various semiconductor devices can be significantly improved. Performance improvements can be obtained in application specific areas like increase in frequency of operation for digital logic, various power MOSFET and IGBT ICS, improvement in refresh time for DRAM's, decrease in programming time for nonvolatile memory, better visual quality including pixel resolution and color sensitivity for imaging ICs, better sensitivity for varactors in tunable filters, higher drive capabilities for JFET's, and a host of other applications. | 01-14-2010 |
20100191903 | MEMORIES FOR ELECTRONIC SYSTEMS | 07-29-2010 |
20100202230 | MEMORIES WITH FRONT END PRECHARGE - Methods, apparatuses and systems of operating digital memory where the digital memory device including a plurality of memory cells receives a command to perform an operation on a set of memory cells, where the set of memory cells contains fewer memory cells than the device as a whole and where the device performs the operation including selectively precharging on the front end of the operation, in response to the received command, only a set of bit lines associated with the set of memory cells. | 08-12-2010 |