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Futatsuya
Hiroki Futatsuya, Akishima JP
| Patent application number | Description | Published |
|---|---|---|
| 20090293039 | METHOD FOR MANUFACTURING A PHOTOMASK - A method for manufacturing a photomask based on design data includes the steps of forming a figure element group including a figure element in a layout pattern on the photomask and a figure element affecting the figure element due to the optical proximity effect, adding identical identification data to a data group indicating an identical figure element group, estimating an influence of the optical proximity effect on the figure element group, generating correction data indicating a corrected figure element in which the influence of the optical proximity effect is compensated for at the time of exposure, creating figure data by associating data having the identical identification data with correction data having the identical identification data, and forming a mask pattern on the photomask using figure data. Thus, the computation time for correction of the layout can be reduced, thereby reducing the production time of the photomask. | 11-26-2009 |
| 20110159417 | METHOD FOR MANUFACTURING A PHOTOMASK - A method for manufacturing a photomask based on design data includes the steps of forming a figure element group including a figure element in a layout pattern on the photomask and a figure element affecting the figure element due to the optical proximity effect, adding identical identification data to a data group indicating an identical figure element group, estimating an influence of the optical proximity effect on the figure element group, generating correction data indicating a corrected figure element in which the influence of the optical proximity effect is compensated for at the time of exposure, creating figure data by associating data having the identical identification data with correction data having the identical identification data, and forming a mask pattern on the photomask using figure data. Thus, the computation time for correction of the layout can be reduced, thereby reducing the production time of the photomask. | 06-30-2011 |
Hiroki Futatsuya, Kawasaki JP
| Patent application number | Description | Published |
|---|---|---|
| 20110312186 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - The semiconductor device manufacturing method comprises the step of transferring patterns formed on a reticle to a semiconductor substrate by an exposure with oblique incidence illumination. In the step of making the exposure with oblique incidence illumination, the exposure is made with an aperture stop | 12-22-2011 |
Masatoshi Futatsuya, Ichinomiya-Shi JP
| Patent application number | Description | Published |
|---|---|---|
| 20090141332 | ELECTROOPTICAL APPARATUS, ELECTRONIC DEVICE, AND APPARATUS AND METHOD FOR DETECTING OUTSIDE LIGHT - An electrooptical apparatus includes a display unit that emits display light, a light emission stopping unit that stops emission of the display light in the display unit, a light receiving unit that receives outside light around the display unit while emission of the display light is stopped, an accumulating unit that accumulates the amount of outside light received by the light receiving unit, and a calculating unit that calculates the light intensity of outside light on the basis of the time taken for the accumulated amount of outside light received to exceed a predetermined threshold. | 06-04-2009 |
Tomoshi Futatsuya, Tokyo JP
| Patent application number | Description | Published |
|---|---|---|
| 20100290292 | SEMICONDUCTOR DEVICE - The present invention provides a semiconductor device having a nonvolatile memory function capable of shortening an erase time and executing data access efficiently. When, under the control of a command register/control circuit, an erase voltage is applied to an embedded erase gate wiring disposed in a memory cell boundary region, and an electrical charge is transferred between a floating gate and an embedded erase gate to thereby perform an erase operation, a read selection voltage is applied to a memory gate line and an assist gate line during the application of the erase voltage to thereby carry out the reading of data. | 11-18-2010 |