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Fung, TW
Chang-Phone Fung, Taipei TW
| Patent application number | Description | Published |
|---|---|---|
| 20110287452 | Test Kit for Detecting Klebsiella Pneumoniae Serotype K1 and Method Using Same - Disclosed are a test kit and method for sensitively and rapidly detecting | 11-24-2011 |
Dein-Run Fung, Taisan Hsiang TW
| Patent application number | Description | Published |
|---|---|---|
| 20090075099 | Waterborne Coating Compositions for Optical-use Polyester film - A water based coating composition containing 2-40 wt % resin, 0.05-30 wt % mixed solution including grafting filler/Si compound/surfactant/polymer and 0.05-10 wt % additives can be used for the production of an optical-use polyester film. The described resin contains about: | 03-19-2009 |
Dein-Run. Fung, Taipei County TW
| Patent application number | Description | Published |
|---|---|---|
| 20080249226 | Waterborne coating compositions for optical-use polyester film - A water based coating composition containing | 10-09-2008 |
| 20110223387 | NON-PVC TYPE CALENDERED POLYOLEFIN SHEET AND THE PROCESS THEREOF - The present invention relates to a non-PVC type calendered polyolefin sheet and the preparation process thereof, characterized in that a polyolefin material composition which is different from polyvinyl chloride (PVC) is processed by the calendering process to produce polyolefin plastic sheets; the process includes that first of all raw materials are evenly blended in a mixer, homogeneously melt-mixed in Banbury mixer, then fully gelled in a roll mill, thereafter calendered in a calender into the sheet which can be pattern-embossed with a set of embossing rolls if necessary, finally the sheet product is cooled down to fix the pattern. | 09-15-2011 |
Ka-Hing Fung, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20110008940 | SELF-ALIGNED V-CHANNEL MOSFET - Forming a high-κ/metal gate field effect transistor using a gate last process in which the channel region has a curved profile thus increasing the effective channel length improves the short channel effect. During the high-κ/metal gate process, after the sacrificial materials between the sidewall spacers are removed, the exposed semiconductor substrate surface at the bottom of the gate trench cavity is etched to form a curved recess. Subsequent deposition of high-κ gate dielectric layer and gate electrode metal into the gate trench cavity completes the high-κ/metal gate field effect transistor having a curved channel region that has a longer effective channel length. | 01-13-2011 |
| 20110147765 | DUMMY STRUCTURE FOR ISOLATING DEVICES IN INTEGRATED CIRCUITS - The present disclosure provides an integrated circuit. The integrated circuit includes a first operational device having a first transistor of a first composition; a second operational device having a second transistor of the first composition; and an isolation transistor disposed between the first and second transistors, the isolation transistor having a second composition different from the first composition. | 06-23-2011 |
| 20110193179 | LIGHTLY DOPED SOURCE/DRAIN LAST METHOD FOR DUAL-EPI INTEGRATION - An integrated circuit device and method for fabricating the integrated circuit device is disclosed. The method involves providing a substrate; forming a gate structure over the substrate; forming an epitaxial layer in a source and drain region of the substrate that is interposed by the gate structure; and after forming the epitaxial layer, forming a lightly doped source and drain (LDD) feature in the source and drain region. | 08-11-2011 |
Ka-Hing Fung, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20080283894 | Forming floating body RAM using bulk silicon substrate - A method for forming Z-RAM cells and the resulting semiconductor structure are provided. The semiconductor structure includes a semiconductor substrate; a dielectric layer on the semiconductor substrate; an opening in the dielectric layer, wherein the semiconductor substrate is exposed through the opening; a semiconductor strip on the dielectric layer and adjacent the opening; a gate dielectric over a surface of the semiconductor strip; a gate electrode over the gate dielectric; and a source/drain region in the semiconductor strip and adjacent the gate electrode. | 11-20-2008 |
| 20090298248 | Two-Step STI Formation Process - A method of forming an integrated circuit structure includes providing a semiconductor substrate; forming a first isolation region in the semiconductor substrate; after the step of forming the first isolation region, forming a metal-oxide-semiconductor (MOS) device at a surface of the semiconductor substrate, wherein the step of forming the MOS device comprises forming a source/drain region; and after the step of forming the MOS device, forming a second isolation region in the semiconductor substrate. | 12-03-2009 |
| 20100144102 | Forming Floating Body RAM Using Bulk Silicon Substrate - A method for forming a semiconductor device is provided. The method comprises providing a semiconductor structure comprising a semiconductor substrate and a dielectric layer on the semiconductor substrate, wherein the dielectric layer has an opening through which the semiconductor substrate is exposed; forming a semiconductor strip on the dielectric layer and adjacent the opening, wherein the semiconductor strip is electrically isolated from the semiconductor substrate; forming a gate dielectric over a portion of the semiconductor strip that is over the dielectric layer; forming a gate electrode over the gate dielectric; and forming a source/drain region in the semiconductor strip. | 06-10-2010 |
| 20110031541 | Two-Step STI Formation Process - A method of forming an integrated circuit structure includes providing a semiconductor substrate; forming a first isolation region in the semiconductor substrate; after the step of forming the first isolation region, forming a metal-oxide-semiconductor (MOS) device at a surface of the semiconductor substrate, wherein the step of forming the MOS device comprises forming a source/drain region; and after the step of forming the MOS device, forming a second isolation region in the semiconductor substrate. | 02-10-2011 |
| 20110193167 | Self-Aligned Two-Step STI Formation Through Dummy Poly Removal - An integrated circuit structure includes a semiconductor substrate including an active region. A first shallow trench isolation (STI) region adjoins a first side of the active region. A gate electrode of a MOS device is over the active region and the first STI region. A source/drain stressor region of the MOS device includes a portion in the semiconductor substrate and adjacent the gate electrode. A trench is formed in the semiconductor substrate and adjoining a second side of the active region. The trench has a bottom no lower than a bottom of the source/drain region. An inter-layer dielectric (ILD) extends from over the gate electrode to inside the trench, wherein a portion of the ILD in the trench forms a second STI region. The second STI region and the source/drain stressor region are separated from each other by, and adjoining, a portion of the semiconductor substrate. | 08-11-2011 |
| 20110212588 | Replacing Symmetric Transistors with Asymmetric Transistors - A semiconductor structure includes a symmetric metal-oxide-semiconductor (MOS) transistor comprising a first and a second asymmetric MOS transistor. The first asymmetric MOS transistor includes a first gate electrode, and a first source and a first drain adjacent the first gate electrode. The second asymmetric MOS transistor includes a second gate electrode, and a second source and a second drain adjacent the second gate electrode. The first gate electrode is connected to the second gate electrode, wherein only one of the first source and the first drain is connected to only one of the respective second source and the second drain. | 09-01-2011 |
| 20110254105 | Strained Semiconductor Device with Recessed Channel - A semiconductor device having a strained channel and a method of manufacture thereof is provided. The semiconductor device has a gate electrode formed over a channel recess. A first recess and a second recess formed on opposing sides of the gate electrode are filled with a stress-inducing material. The stress-inducing material extends into an area wherein source/drain extensions overlap an edge of the gate electrode. In an embodiment, sidewalls of the channel recess and/or the first and second recesses may be along {111} facet planes. | 10-20-2011 |
Kuan-Zong Fung, Taipei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110043964 | CERAMIC POWDER COMPOSITION, CERAMIC MATERIAL, AND MULTI-LAYER CERAMIC CAPACITOR FABRICATED THEREBY - A ceramic powder composition, ceramic material, and a multi-layer ceramic capacitor fabricated thereby are provided. The ceramic powder composition includes a main ingredient and an accessory ingredient. The main ingredient is in an amount of 95 to 99 mol %, and includes BaTiO | 02-24-2011 |
Kuan-Zong Fung, Taoyuan County TW
| Patent application number | Description | Published |
|---|---|---|
| 20110159445 | Method for Making a Texture on a Transparent Conductive Film of a Solar Cell - Disclosed is a method for making a texture on a face of a transparent conductive film coated on a glass substrate. The method includes the steps of forming a texture on the face of the glass substrate and coating the transparent conductive film on the texture formed on the face of the glass substrate. | 06-30-2011 |
Ren-Chieh Fung, Taichung City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110261348 | Optical Calibration and Testing Device for Machine Tools - An optical calibration and testing device for machine tools includes a light source unit, a beam splitter, and at least one photo detector. The light source emits a laser light hitting the beam splitter and is split into two beams. One is perpendicular to the foundation of the light source unit, and the other is parallel with the foundation so as to test straightness, inclination angle, verticalness, vertical column inclination, vertical column parallelism and guide bar inclination of a machine tool. If there is no tested error, the position of the testing light spot coincides with that of the initial light spot. If there is an error, the position of testing light spot varies according to the error. | 10-27-2011 |