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Funaba
Masashi Funaba, Hokkaido JP
| Patent application number | Description | Published |
|---|---|---|
| 20110045300 | GRAPHITE COMPLEX AND MANUFACTURING METHOD THEREOF - A graphite complex has a pyrolytic graphite sheet and a graphite layer. The pyrolytic graphite sheet is made by firing a polymer film. The graphite layer contains graphite powder as the main ingredient and is directly joined to the pyrolytic graphite sheet. | 02-24-2011 |
| 20110265980 | GRAPHITE SHEET AND HEAT TRANSFER STRUCTURE USING SAME - A graphite sheet preventing leakage of a heat radiating member when a fluid heat radiating member such as grease is used and improving heat radiation performance is provided. A graphite sheet includes a first main surface and a second main surface opposite to the first main surface and has a large anisotropic thermal conductivity in a main surface direction. The graphite sheet includes a first concave portion provided on the first main surface and having a first bottom surface, a second concave portion provided on the second main surface and having a second bottom surface, a thin film portion formed in a region in which the first bottom surface and the second bottom surface are overlapped with each other, and a connecting hole penetrating the thin film portion and allowing the first concave portion and the second concave portion to communicate with each other. | 11-03-2011 |
Seiji Funaba, Hitachinaka-Shi JP
| Patent application number | Description | Published |
|---|---|---|
| 20110031939 | Discharge Circuit for Smoothing Capacitor of DC Power Supply - A discharge circuit for a DC power supply smoothing capacitor that is used in a power conversion device that supplies DC power via a switch to the DC power supply smoothing capacitor and an inverter, includes; a resistor that discharges charge in the capacitor; a switch connected in series with the resistor, that either passes or intercepts discharge current flowing from the capacitor to the resistor; a measurement circuit that measures a terminal voltage of the capacitor; and a control circuit that controls continuity and discontinuity of the switch; wherein the control circuit, after having made the switch continuous and starting discharge of the capacitor by the resistor, if a terminal voltage of the capacitor as measured by the measurement circuit exceeds a voltage decrease characteristic set in advance, makes the switch discontinuous and stops discharge by the resistor. | 02-10-2011 |
Seiji Funaba, Sagamihara JP
| Patent application number | Description | Published |
|---|---|---|
| 20090245424 | SEMICONDUCTOR DEVICE, MEMORY DEVICE AND MEMORY MODULE HAVING DIGITAL INTERFACE - An object of the present invention is to reduce jitter dependent on data patterns by an interface receiver. Another object of the present invention is to provide an LSI capable of automatically adjusting a delay time for jitter reduction so as to be able to control its setting for each device. Since the jitter dependent on the data patterns can be expected according to how the previous state is being placed, the state of data received by the receiver is held, and the timing provided to fetch input data is adjusted according to the held state and the input data. As a control mechanism lying in the receiver, for determining a delay time dependent on the form of mounting, a driver transmits and receives pulse data set at one-cycle intervals and pulse data set at two-cycle intervals as test patterns. The receiver has an automatic control mechanism for determining a delay time optimal to a system from the difference between a rising time of each of pulses different in pulse width and its falling time. | 10-01-2009 |
Seiji Funaba, Kokubunji JP
| Patent application number | Description | Published |
|---|---|---|
| 20090115442 | Semiconductor integrated circuit and electronic device - A dummy wiring | 05-07-2009 |
Seiji Funaba, Tokyo JP
| Patent application number | Description | Published |
|---|---|---|
| 20080203554 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A COC DRAM including a plurality of stacked DRAM chips is mounted on a motherboard by using an interposer. The interposer includes a Si unit and a PCB. The Si unit includes a Si substrate and an insulating-layer unit in which wiring is installed. The PCB includes a reference plane for the wiring in the Si unit. The wiring topology between a chip set and the COC DRAM is the same for every signal. Accordingly, a memory system enabling a high-speed operation, low power consumption, and large capacity is provided. | 08-28-2008 |
Seiji Funaba, Ibaraki JP
| Patent application number | Description | Published |
|---|---|---|
| 20120020136 | Electric Power Conversion System - A power conversion system according to the present invention includes: an inverter circuit unit that converts a direct current power supplied from a direct current source into an alternating current power, the direct current power being supplied to the inverter circuit through a contactor that conducts and interrupts the direct current; a capacitor that smoothes the direct current power; a discharge circuit unit that is connected to the capacitor in parallel, and that includes a discharge resistor for discharging a charge stored in the capacitor and a switching element for the discharge resistor, being connected in series to the discharge resistor; a voltage detection circuit unit that detects voltage between both terminals of the capacitor; a first discharge control circuit that includes a first microcomputer, and that outputs a control signal to control switching of the switching element for discharging; and a second discharge control circuit that outputs an interruption signal to interrupt the switching element for the discharge resistor. | 01-26-2012 |