Patent application number | Description | Published |
20080203584 | Stacked-type semiconductor package - Corresponding parts to a first path portion in a first signal transmission path to a first semiconductor chip are an interconnection member and a second path portion a second signal transmission path to a second semiconductor chip and are not formed on the first tape. An electric length of the second signal transmission path is allowed to be adjusted independently of the first tape, so that the electric length of the second signal transmission path can be easily made equal to or substantially equal to that of the first signal transmission path. | 08-28-2008 |
20080224311 | SEMICONDUCTOR DEVICE - A semiconductor device is disclosed including a data family pad layout wherein an effort is made to contrive layouts of a power lead wire and a ground lead wire to minimize effective inductance in priority to a length of a lead wire between a pad and a solder ball land of a semiconductor chip. Pad layouts are arrayed in two rows and one unit of the pad layout is configured such that a data power source and ground are adjacent to each other or one data is inserted between the data power source and the ground. Such configurations decrease mutual inductance between the data power sources and increase mutual inductance between the data power source and the ground causing reduction in effective inductance between the data power source and the ground with the resultant minimization of power and ground noises. | 09-18-2008 |
20090001548 | Semiconductor package - A semiconductor package which includes: a semiconductor chip which includes a signal terminal for inputting and outputting electrical signals and a ground terminal; and a package substrate which includes a semiconductor chip mounting surface on which the semiconductor chip is mounted, and a terminal electrode forming surface on which a signal terminal electrode electrically connected to the signal terminal and a ground terminal electrode electrically connected to the ground terminal are arranged in an array pattern, wherein: on the semiconductor chip mounting surface, there is provided a first signal wiring connected to the signal terminal, a ground wiring connected to the ground terminal, and a ground conductive layer connected to the ground wiring and is provided in a planar pattern in an area excluding the forming area of the first signal wiring; on the terminal electrode forming surface, there is provided a second signal wiring connected to the signal terminal electrode, and a ground fine wiring connected to the ground terminal electrode; and the first signal wiring and the second signal wiring are connected via a conductor filled in a signal through hole penetrating the package substrate, and the ground conductive layer and the ground fine wiring are connected via a conductor filled in a ground through hole penetrating the package substrate. | 01-01-2009 |
20090009213 | Calibration circuit, semiconductor device including the same, and data processing system - A calibration circuit includes: replica buffers; an up-down counter that changes impedance codes of the replica buffers; latch circuits each holding the impedance codes; an end-determining circuit that activates the latch circuits in response to a completion of impedance adjustments of the replica buffers; and a 32 tCK cycle counter that forcibly activates the latch circuits in response to a lapse of a predetermined period since issuance of the calibration command. Thereby, even when the adjustment is not completed during one calibration period, a subsequent calibration operation can be executed from a previous point. | 01-08-2009 |
20100097096 | Calibration circuit, semiconductor device including the same, and data processing system - A semiconductor device adjusting an impedance level of an output buffer, includes a replica buffer circuit including a circuit configuration substantially identical to the output buffer, a counter circuit changing an impedance code to vary an impedance level of the replica buffer, a latch circuit temporarily holding the impedance code in response to a control signal, and an end-determining circuit producing the control signal in response to a lapse of a predetermined period from issuance of a calibration command, irrespective of a fact that the replica buffer has not yet reached a desirable impedance level. | 04-22-2010 |
20100309706 | Load reduced memory module and memory system including the same - A memory module includes a plurality of memory chips, a plurality of data register buffers, and a command/address/control register buffer mounted on a module PCB. The data register buffers perform data transfers with the memory chips. The command/address/control register buffer performs buffering of a command/address/control signal and generates a control signal. The buffered command/address/control signal is supplied to the memory chips, and the control signal is supplied to the data register buffers. According to the present invention, because line lengths between the data register buffers and the memory chips are shortened, it is possible to realize a considerably high data transfer rate. | 12-09-2010 |
20100312925 | Load reduced memory module - A memory module includes a plurality of data connectors provided along a long side of a module substrate, a plurality of memory chips and a plurality of data register buffers mounted on the module substrate, a data line that connects the data connectors and the data register buffers, and data lines that connect the data register buffers and the memory chips. Each of the data register buffers and a plurality of data connectors and a plurality of memory chips corresponding to the data register buffer are arranged side by side in a direction of a short side of the module substrate. According to the present invention, because each line length of the data lines is considerably shortened, it is possible to realize a considerably high data transfer rate. | 12-09-2010 |
20100312956 | Load reduced memory module - A memory module includes a plurality of memory chips and a plurality of data register buffers mounted on the module substrate. At least two memory chips are allocated to each of the data register buffers. Each of the data register buffers includes M input/output terminals (M is a positive integer equal to or larger than 1) that are connected to the data connectors via a first data line and N input/output terminals (N is a positive integer equal to or larger than 2M) that are connected to corresponding memory chips via second and third data lines, so that the number of the second and third data lines is N/M times the number of the first data lines. According to the present invention, because the load capacities of the second and third data lines are reduced by a considerable amount, it is possible to realize a considerably high data transfer rate. | 12-09-2010 |
20110248742 | Calibration circuit, semiconductor device including the same, and data processing system - A method includes issuing a calibration command and performing a calibration operation in response to the calibration command. The calibration operation includes adjusting an impedance of a first replica buffer with updating a first code, the first replica buffer being substantially identical in circuit configuration to one of pull-up and pull-down circuits included in an output buffer, adjusting impedance of a second replica buffer with updating a second code, the second replica buffer being substantially identical in circuit configuration to the other of the pull-up and pull-down circuits included in the output buffer, controlling a first latch circuit to hold the first code when the impedance of the first replica buffer reaches a first level, and controlling a second latch circuit to hold the second code when the impedance of the second replica buffer reaches a second level. | 10-13-2011 |
20120250264 | MEMORY MODULE HAVING MEMORY CHIP AND REGISTER BUFFER - Disclosed herein is a memory module that includes a register buffer and a memory chip each mounted on a module substrate. Each of the command address output terminals belonging to the first group provided on the register buffer is connected to an associated one of the command address input terminals belonging to the first group provided on the memory chip through associated ones of the plurality of contact plugs and the first wiring layer. Each of the command address output terminals belonging to the second group provided on the register buffer is connected to an associated one of the command address input terminals belonging to the second group provided on the memory chip through associated ones of the plurality of contact plugs and the second wiring layer. | 10-04-2012 |
20130135916 | MEMORY MODULE INCLUDING PLURAL MEMORY DEVICES AND DATA REGISTER BUFFER - Disclosed herein is a memory module that includes a module substrate, data connectors, memory devices, and data register buffers. A first main surface of the module substrate has first and second memory mounting areas. One of the first and second main surfaces of the module substrate has a register mounting area located between the first and second memory mounting areas in a planner view. The memory devices include a plurality of first memory devices that are mounted on the first memory mounting area and a plurality of second memory devices that are mounted on the second memory mounting area. The data register buffers are mounted on the register mounting area. The data register buffers transfers write data supplied from the data connectors to the memory devices, and transfers read data supplied from the memory devices to the data connectors. | 05-30-2013 |
20130138898 | MEMORY MODULE INCLUDING PLURAL MEMORY DEVICES AND COMMAND ADDRESS REGISTER BUFFER - Disclosed herein is a memory module that includes a plurality of command address connectors formed on the module substrate, a plurality of memory devices mounted on the module substrate, and a plurality of command address register buffers mounted on the module substrate. The command address connectors receive a command address signal from outside. The memory devices include a plurality of first memory devices and a plurality of second memory devices. The command address register buffers include a first command address register buffer that supplies the command address signal to the first memory devices and a second command address register buffer that supplies the command address signal to the second memory devices. | 05-30-2013 |
20130215659 | LOAD REDUCED MEMORY MODULE AND MEMORY SYSTEM INCLUDING THE SAME - A device includes a printed circuit board, a clock connector provided on the printed circuit board and configured to be supplied with a first clock signal, a first register buffer provided on the printed circuit board, coupled to the clock connector and, including a first clock generator that produces a second clock signal in response to the first clock signal, a plurality of data connectors, provided on the printed circuit board, a plurality of memory chips each provided on the printed circuit board and including a first data terminal, and a plurality of second register buffers each provided on the printed circuit board independently of the first register buffer. | 08-22-2013 |