| Patent application number | Description | Published |
|---|
| 20090040676 | CIRCUIT FOR DETECTING POWER SUPPLY VOLTAGE DROP - Provided is a circuit for detecting power supply voltage drop having a small circuit scale. An NMOS transistor ( | 02-12-2009 |
| 20090146499 | POWER SUPPLY SWITCHING CIRCUIT - In a power supply switching circuit, a transistor that switches to a highest voltage is formed of an enhancement type PMOS transistor, and transistors that switch other voltages are each formed of a depletion type NMOS transistor. A signal for controlling a gate of each of the transistors is input through a level shifter. The depletion type NMOS transistor does not operate in a bipolar manner even if a source voltage thereof reaches a power supply voltage VPP | 06-11-2009 |
| 20090167410 | POWER SUPPLY SWITCHING CIRCUIT - Provided is a power supply switching circuit capable of efficiently supplying a desired voltage among a plurality of voltages to a load. In the case of a P-type semiconductor substrate, N-type MOS transistors are provided between a load and an AC adapter and between the load and a battery, and hence no parasitic diode exists between the load and the AC adapter or the battery, resulting in no current path due to the parasitic diode. Thus, when the AC adapter and the battery are connected to the power supply switching circuit, the N-type MOS transistor is turned off, whereby the current path between the battery and the load is cut off completely and the N-type MOS transistor is turned on. Accordingly, the battery cannot supply a voltage to the load while only the AC adapter can supply a voltage to the load. | 07-02-2009 |
| 20090184753 | CHARGE PUMP CIRCUIT - Provided is a charge pump circuit capable of shortening a settling time. When a boosted voltage (Vout) becomes high to be equal to or larger than an overshoot voltage, a transistor (T1) is turned on and an output terminal of the charge pump circuit is discharged. Accordingly, it is easy to reduce the boosted voltage (Vout) after an occurrence of an overshoot, and a period of time in which the boosted voltage (Vout) decreases from a voltage after the occurrence of the overshoot to a desired voltage is shortened, leading to a reduction in a settling time. | 07-23-2009 |
| 20090190407 | SEMICONDUCTOR MEMORY DEVICE - Provided is a semiconductor memory device, which realizes characteristic evaluation even in a case where a threshold voltage is a negative potential by a test method which is similar to a case of a positive potential. The semiconductor memory device includes a plurality of memory cells for storing data. When a test signal is input, the semiconductor memory device changes from a normal mode to a test mode for evaluating characteristics of the plurality of memory cells. The semiconductor memory device also includes: a memory cell selecting portion for selecting a memory cell; a constant voltage portion for generating a reference voltage; a constant current portion for generating a reference current; an X switch voltage switching control circuit for supplying one of an X selection signal and a voltage signal input from an external terminal to a gate of the memory cell; a Y switch portion for supplying the reference current to a drain of the memory cell selected by a Y selection signal; a comparator for detecting whether or not a drain voltage that is a voltage of the drain has exceeded the reference voltage; and a decision level changing portion for adjusting a current value of the reference current and a voltage value of the reference voltage so as to change a decision level of the comparator based on a control signal in the test mode. | 07-30-2009 |
| 20090195284 | SEMICONDUCTOR DEVICE EQUIPPED WITH A PULL-DOWN CIRCUIT - Provided is a semiconductor device equipped with a pull-down circuit capable of reducing its area. The pull-down circuit is formed of a depletion type NMOS transistor in which a gate thereof is connected to a ground potential, and an enhancement type NMOS transistor in which a gate and a drain thereof are connected to a source of the depletion type NMOS transistor and a source thereof is connected to the ground potential. An overdrive voltage of the depletion type NMOS transistor is reduced by a threshold voltage of the enhancement type NMOS transistor, whereby a size of the depletion type NMOS transistor can be reduced. Accordingly, an area of the pull-down circuit can be reduced. | 08-06-2009 |
| 20090201006 | CONSTANT CURRENT CIRCUIT - Provided is a constant current circuit capable of supplying a stable constant current. Even when K values of NMOS transistors vary due to manufacturing fluctuations in semiconductor devices, a voltage generated across a resistor is always a threshold voltage difference between the NMOS transistors, and thus hardly varies. Even when the K values of the NMOS transistors vary due to a change in temperature, the voltage generated across the resistor is always the threshold voltage difference between the NMOS transistors, and thus hardly varies. | 08-13-2009 |
| 20090213665 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - Provided is a nonvolatile semiconductor memory device which reads out a memory cell at high speed. A minute current source ( | 08-27-2009 |
| 20100188124 | POWER-ON RESET CIRCUIT - Provided is a power-on reset circuit suitable for a semiconductor device that operates at a low supply voltage. When a supply voltage (VDD) becomes higher than a first output circuit reversal threshold voltage (Vz) after a reset signal is output, a first control circuit ( | 07-29-2010 |
| 20100188137 | BOOSTING CIRCUIT - Provided is a boosting circuit having a small circuit scale. When a node (Vg) is reset by a reset transistor (M | 07-29-2010 |
| 20100213932 | MAGNETIC SENSOR CIRCUIT - Provided is a magnetic sensor circuit capable of a low-voltage operation, which comprises a Hall element and a magnetic offset cancellation circuit for the Hall element. In the magnetic sensor circuit using the Hall element, at the time of turning on transmission gates for switching connections between input terminals of an amplifier circuit in the magnetic offset cancellation circuit and electrodes of the Hall element in order to cancel a magnetic offset of the Hall element, gates of N-channel transistors in the transmission gates are set at voltages higher than a power supply voltage by a drive circuit. | 08-26-2010 |
| 20100258706 | PHOTODETECTOR CIRCUIT AND ELECTRONIC DEVICE - Provided is a photodetector circuit having significantly low current consumption. The photodetector circuit includes two opposing P-channel metal oxide semiconductor (MOS) transistors each including a gate connected to a drain of the opposing P-channel MOS transistor. The drain of one of the P-channel MOS transistors is discharged with an ON-state current of an N-channel MOS transistor which is turned ON with a voltage generated in a photoelectric element. The drain of the other of the P-channel MOS transistors is discharged with an ON-state current of a depletion type N-channel MOS transistor including a gate to which a voltage of a reference power supply terminal is input, and a source to which the voltage generated in the photoelectric element is input. | 10-14-2010 |
| 20110001513 | CMOS INPUT BUFFER CIRCUIT - Provided is a complementary metal oxide semiconductor (CMOS) input buffer circuit that is capable of lower voltage operation with lower current consumption. The CMOS input buffer circuit includes: a depletion type NMOS transistor including a drain connected to a power supply terminal (VDD), and a gate connected to an output terminal; a PMOS transistor including a source connected to a source of the depletion type NMOS transistor, a drain connected to the output terminal, and a gate connected to an input terminal; and an NMOS transistor including a source connected to a reference terminal (GND), a gate connected to the input terminal, and a drain connected to the output terminal. | 01-06-2011 |
| 20110109364 | INPUT CIRCUIT - Provided is an input circuit having hysteresis characteristics that is capable of operating in a wide range of power supply voltage conditions while suppressing power supply voltage dependence of a hysteresis voltage and a response speed. The input circuit is provided with: a circuit for obtaining a small hysteresis voltage under the condition of low power supply voltage (formed of PMOS transistors ( | 05-12-2011 |
