Patent application number | Description | Published |
20080212373 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE WITH A STACKED GATE INCLUDING A FLOATING GATE AND A CONTROL GATE - A semiconductor integrated circuit device includes first and second nonvolatile semiconductor memories. The first memory has first and second select transistors and first memory cell transistors. The first memory cell transistor has a first floating gate on a first gate insulating film and a first control gate on a first inter-gate insulating film. The second memory has a third select transistor and a second memory cell transistor. The second memory cell transistor has a second floating gate on a second gate insulating film and a second control gate on a second inter-gate insulating film. The first and second gate insulating films have the same film thickness. The first and second floating gates have the same film thickness. The first and second inter-gate insulating films have the same film thickness. The first and second control gates have the same film thickness. | 09-04-2008 |
20080219054 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING OF THE SAME - A semiconductor memory device includes a plurality of active areas each extending in a first direction and including a memory cell string which includes select transistors and memory cells, current paths of which are connected in series, a first extension portion which is provided between one-side terminal end portions of two active areas neighboring in a second direction that crosses the first direction, and a second extension portion which is provided between other-side terminal end portions of the two active areas neighboring in the second direction, the first and second extension portions connecting the two active areas in a loop configuration. | 09-11-2008 |
20080251881 | SEMICONDUCTOR DEVICE WITH DOUBLE BARRIER FILM - A semiconductor device comprising a first insulation layer, a second insulation layer, a first barrier film, a second barrier film, a diffusion layer. The device further comprises an upper contact hole, a lower contact hole, and a contact plug. The upper contact hole penetrates the second insulation layer and has a bottom in the second barrier film. The bottom has a width greater than a trench made in the first insulation layer, as measured in a direction crossing the widthwise direction of the trench. The lower contact hole penetrates the first insulation layer and first barrier film, communicates with the first contact hole via the trench and is provided on the diffusion layer. The upper portion of the lower contact hole has the same width as the trench. The contact plug is provided in the upper contact hole and lower contact hole. | 10-16-2008 |
20080283839 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREOF - A non-volatile semiconductor storage device includes a substrate, a first insulating layer formed on the substrate, a semiconductor layer formed of polysilicon on the first insulating layer, a pair of conductor regions formed on the first insulating layer to pass through the semiconductor layer and to sandwich a part of the semiconductor layer, and formed of a metal or a silicide, a tunnel layer formed on the part of the semiconductor layer sandwiched between the pair of conductor regions, a charge storage layer formed on the tunnel layer, a second insulating layer formed on the charge storage layer, and a control gate formed on the second insulating layer. | 11-20-2008 |
20080315280 | SEMICONDUCTOR MEMORY DEVICE HAVING MEMORY CELL UNIT AND MANUFACTURING METHOD THEREOF - A semiconductor memory device includes a silicon substrate including a first region which has a buried insulating layer below a single-crystal silicon layer and a second region which does not have the buried insulating layer below the single-crystal silicon layer, at least one memory cell transistor which has a first gate electrode, the first gate electrode being provided on the single-crystal silicon layer in the first region, and at least one selective gate transistor which has a second gate electrode and is provided on the single-crystal silicon layer in the first region. The one selective gate transistor is provided in such a manner that a part of the second gate electrode is placed on the single-crystal silicon layer in the second region. | 12-25-2008 |
20090003071 | SEMICONDUCTOR STORAGE DEVICE AND READ VOLTAGE CORRECTION METHOD - A semiconductor memory device comprises a semiconductor memory, a corrected voltage storage circuit which stores a corrected voltage produced by correcting a read voltage of the semiconductor memory, and a memory controller which reads the corrected voltage from the corrected voltage storage circuit and performs a read operation of the semiconductor memory using the corrected voltage. | 01-01-2009 |
20090010074 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes: a semiconductor layer provided on an insulating substrate or an insulating layer; active areas each defined in the semiconductor layer with a device insulating film buried therein; and NAND cell units formed on the active areas, each NAND cell unit including a plurality of electrically rewritable and non-volatile memory cells connected in series, both ends of each NAND cell unit being coupled to a source line and a bit line, wherein the device has such a carrier discharging mode as to discharge channel carriers in the NAND cell unit to at least one of the source line and the bit line. | 01-08-2009 |
20090011559 | NON-VOLATILE SEMICONDUCTOR MEMORY AND METHOD FOR MANUFACTURING A NON-VOLATILE SEMICONDUCTOR MEMORY - An non-volatile semiconductor memory having a linear arrangement of a plurality of memory cell transistors, includes: a first semiconductor layer having a first conductivity type; a second semiconductor layer provided on the first semiconductor layer to prevent diffusion of impurities from the first semiconductor layer to regions above the second semiconductor layer; and a third semiconductor layer provided on the second semiconductor layer, including a first source region having a second conductivity type, a first drain regions having the second conductivity type and a first channel region having the second conductivity type for each of the memory cell transistors. | 01-08-2009 |
20090016108 | NONVOLATILE SEMICONDUCTOR MEMORY - A method of reading out data from nonvolatile semiconductor memory including the steps of applying a first voltage to a bit line contact; applying a second voltage to a source line contact, wherein the second voltage is substantially smaller than the first voltage; applying a third voltage gates of third and fourth select gate transistors, the third voltage configured to bring the third and fourth select gate transistors into conduction; applying a fourth voltage to gates of the plurality of memory cell transistors of a second memory cell unit, the fourth voltage configured to bring the plurality of memory cell transistors of the second memory cell unit into conduction or not, depending on the data that is stored in the memory cell unit; and applying a fifth voltage to gates of the plurality of memory cell transistors of a first memory cell unit, the fifth voltage configured to bring the plurality of memory cell transistors of the first memory cell unit into conduction; wherein the fifth voltage is bigger than the fourth voltage. | 01-15-2009 |
20090021982 | SEMICONDUCTOR MEMORY DEVICE AND DATA ERASE METHOD THEREOF - A semiconductor memory device includes a memory cell array which includes a plurality of memory cell strings each including a plurality of memory cells and a first dummy cell, which have current paths connected in series at one end and the other end thereof, a plurality of first and second select transistors, a source line, and a bit line, wherein the first dummy cell is disposed on the source line side such that one end and the other end of the current path thereof are connected between the first select transistor and the memory cell, and a threshold voltage of the first dummy cell is higher than a neutral threshold voltage. | 01-22-2009 |
20090052242 | NAND TYPE NONVOLATILE SEMICONDUCTOR MEMORY - A memory includes n-numbered memory cells (n is an integer of not less than 3) and a driver which applies a first voltage to a control gate electrode of a selected first memory cell in the n-numbered memory cells, applies a second voltage lower than the first voltage to a control gate electrode of a second memory cell adjacent to the first memory cell, and applies a third voltage lower than the second voltage to control gate electrodes of third memory cells other than the first and second memory cells at the time of programming. The first, second and third voltages have values not less than a value for turning on the n-numbered memory cells regardless of their threshold voltages. | 02-26-2009 |
20090080250 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND OPERATION METHOD THEREOF - A multi-valued nonvolatile semiconductor storage device and an operation method thereof capable of setting a plurality of positive levels having positive threshold voltages and a plurality of negative levels having negative threshold voltages for storing information in a charge storage layer is provided. According to one aspect, there is provided a nonvolatile semiconductor storage device which comprises a storage element provided on a first surface of a semiconductor layer and including a charge storage layer provided with a plurality of positive levels having positive threshold voltages and a plurality of negative levels having negative threshold voltages to store information, and a back electrode provided on a second surface of the semiconductor layer to be opposite to the storage element, the back electrode being configured to apply a voltage which converts information stored in the negative level of the charge storage layer to information having a positive threshold voltage. | 03-26-2009 |
20090090959 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A first lamination part includes: a charge accumulation layer provided on the respective sidewalls of laminated first conductive layers and accumulating charges; and a first semiconductor layer provided in contact with the fourth insulation layer and formed to extend to the lamination direction. A second lamination part includes a second semiconductor layer provided in contact with the first semiconductor layer. A third lamination part includes: a plurality of first contact layers formed in contact with the respective second lamination part, extending to a first direction perpendicular to the lamination direction, and in line with each other along a second direction perpendicular to the first direction; and a plurality of contact plug layers formed in contact with any one of the first contact layers and extending to the lamination direction. The contact plug layers are arranged at different positions relative to each other in the first direction. | 04-09-2009 |
20090097309 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE, AND METHOD FOR CONTROLLING NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - According to an aspect of the present invention, there is provided, a nonvolatile semiconductor storage device including: a substrate; a stacked portion that includes a plurality of conductor layers and a plurality of insulation layers alternately stacked on the substrate, at least one layer of the plurality of conductor layers and the plurality of insulation layers forming a marker layer; a charge accumulation film that is formed on an inner surface of a memory plug hole that is formed in the stacked portion from a top surface to a bottom surface thereof; and a semiconductor pillar that is formed inside the memory plug hole through the charge accumulation film. | 04-16-2009 |
20090101960 | SEMICONDUCTOR MEMORY DEVICE - According to an aspect of the present invention, there is provided a semiconductor memory device including: a semiconductor substrate having: a contact region; a select gate region; and a memory cell region; a first element isolation region formed in the contact region and having a first depth; a second element isolation region formed in the select gate region and having a second depth; and a third element isolation region formed in the memory cell region and having a third depth which is smaller than the first depth. | 04-23-2009 |
20090129158 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE INCLUDING NAND-TYPE FLASH MEMORY AND THE LIKE - A nonvolatile semiconductor memory device is provided with a memory cell array, a judgment potential correction circuit, and a readout circuit. In the memory cell array, a plurality of memory cells are arranged in a matrix form, and the array includes a first memory cell as a readout object and a second memory cell disposed adjacent to the first memory cell. The judgment potential correction circuit corrects a judgment potential based on a threshold value of the second memory cell. The readout circuit reads the first memory cell as the readout object by use of the corrected judgment potential. | 05-21-2009 |
20090230450 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE - A non-volatile semiconductor storage device includes: a memory cell area in which a plurality of electrically rewritable memory cells are formed; and a peripheral circuit area in which transistors that configure peripheral circuits to control the memory cells are formed. The memory cell area has formed therein: a semiconductor layer formed to extend in a vertical direction to a semiconductor substrate; a plurality of conductive layers extending in a parallel direction to, and laminated in a vertical direction to the semiconductor substrate; and a property-varying layer formed between the semiconductor layer and the conductive layers and having properties varying depending on a voltage applied to the conductive layers. The peripheral circuit area has formed therein a plurality of dummy wiring layers that are formed on the same plane as each of the plurality of conductive layers and that are electrically separated from the conductive layers. | 09-17-2009 |
20090250768 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device according to the present invention includes: a first transistor formed on a semiconductor substrate | 10-08-2009 |
20090279356 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A memory includes first selective transistors connected between one end of cell strings and bit lines; second selective transistors connected between the other end of the cell strings and a cell source line; a dummy cell string; a first dummy selective transistor connected between one end of the dummy cell string and a dummy bit line and whose gate is connected to a first selective gate line; a second dummy selective transistor connected between the other end of the dummy cell string and the cell source line and whose gate is connected to a second selective gate line, wherein at a time of writing in a selected memory cell, a voltage of a first dummy bit line selected is driven to a different voltage from a voltage of an unselected bit line, and any of the dummy cell transistors connected to the first dummy bit line is written. | 11-12-2009 |
20090310422 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE - A controller repeats an erase operation, an erase verify operation, and a step-up operation. A first storage unit stores a value of an erase start voltage applied first as an erase voltage when a series of erase operations are executed. A second storage unit stores a value of an erase completion voltage which is an erase voltage when erasure of data is finished in the erase operation and the erase verify operation. A first comparator compares the erase completion voltage with the erase start voltage each time the erase operation is executed. When the first comparator determines that the erase completion voltage is larger than the erase start voltage, a counter counts up a count value. When the count value becomes larger than a predetermined value, a second comparator updates a value of the erase start voltage stored in the first storage unit. | 12-17-2009 |
20090323432 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes a memory cell which stores data and which is capable of being rewritten electrically, a bit line which is connected electrically to one end of a current path of the memory cell, a control circuit which carries out a verify operation to check a write result after data is written to the memory cell, and a voltage setting circuit which sets a charging voltage for the bit line in a verify operation and a read operation and makes a charging voltage in a read operation higher than a charging voltage in a verify operation. | 12-31-2009 |
20100052017 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor memory device includes a first block having first memory cells and first select transistors, a second block having second memory cells and second select transistors, and arranged adjacent to the first block in a first direction, the second select transistor being arranged to face the first select transistor and commonly having a diffusion region with the first select transistor, a first interconnection layer provided on the diffusion region between the first and second blocks and extending in a second direction, and a second interconnection layer having a first portion provided in contact with an upper portion of the first interconnection layer and extending to a portion outside the first interconnection layer, and a second portion extending in the second direction and connected to the first portion in a portion outside a portion on the first interconnection layer. | 03-04-2010 |
20100091566 | NAND FLASH MEMORY - In a state in which a first and second selection gate transistors are turned off and a first voltage is applied to a control gate of a second memory cell transistor which is connected to a source line side of a first memory cell transistor selected from among the memory cell transistors and which is to be cut off, a second voltage which is higher than the first voltage and which causes a plurality of third memory cell transistors remaining unselected in the memory cell transistors to conduct is applied to control gates of the third memory cell transistors, and thereafter a threshold voltage of the first memory cell transistor is changed to a threshold voltage higher than the first threshold voltage corresponding to the erase state by applying a third voltage which is higher than the second voltage to a control gate of the first memory cell transistor. | 04-15-2010 |
20100105177 | NONVOLATILE SEMICONDUCTOR MEMORY WITH RESISTANCE ELEMENTS AND METHOD OF MANUFACTURING THE SAME - A nonvolatile semiconductor memory of an aspect of the present invention comprises a memory cell transistor and a resistance element arranged on a semiconductor substrate. The memory cell transistor includes a floating gate electrode constituted of a first conductive material arranged on a gate insulating film on a surface of the semiconductor substrate, an inter-gate insulating film arranged on the floating gate electrode, a control gate electrode arranged on the inter-gate insulating film, and a source/drain diffusion layer provided in the semiconductor substrate. The resistance element includes an element isolation insulating layer arranged in the semiconductor substrate and including a depression, and a resistor constituted of a second conductive material filling up the depression. An impurity concentration of the second conductive material is lower than that of the first conductive material. | 04-29-2010 |
20100127320 | NONVOLATILE SEMICONDUCTOR MEMORY - Two diffusion layers are provided in an element area. A tunnel insulating film is provided on the surface of the element area between the two diffusion layers. A charge storage layer is provided on the tunnel insulating film. A first insulator provided on the upper surface of the charge storage layer. An inter-electrode insulating film provided on the first insulator, on the side surface of the charge storage layer in a first direction and on the isolation insulating film. And a control gate electrode extends in the first direction and covers the charge storage layer via the first insulator and the inter-electrode insulating film. The first insulator is thicker than the inter-electrode insulating film, and the inter-electrode insulating film has a first slit on the first insulator. | 05-27-2010 |
20100159657 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor memory device includes: a semiconductor substrate, on which an impurity diffusion layer is formed in a cell array area; a gate wiring stack body formed on the cell array area, in which multiple gate wirings are stacked and separated from each other with insulating films; a gate insulating film formed on the side surface of the gate wiring stack body, in which an insulating charge storage layer is contained; pillar-shaped semiconductor layers arranged along the gate wiring stack body, one side surfaces of which are opposed to the gate wiring stack body via the gate insulating film, each pillar-shaped semiconductor layer having the same conductivity type as the impurity diffusion layer; and data lines formed to be in contact with the upper surfaces of the pillar-shaped semiconductor layers and intersect the gate wirings. | 06-24-2010 |
20100173471 | NONVOLATILE SEMICONDUCTOR MEMORY AND FABRICATION METHOD FOR THE SAME - A nonvolatile semiconductor memory includes a memory cell transistor including a first floating gate electrode layer formed on a first tunneling insulating film, a first inter-gate insulating film, a first and a second control gate electrode layer, and a first metallic silicide film; a high voltage transistor including a high voltage gate electrode layer formed on the high voltage gate insulating film, a second inter-gate insulating film having an aperture, a third and a fourth control gate electrode layer, and a second metallic silicide film; a low voltage transistor including a second floating gate electrode layer formed on the second tunneling insulating film, a third inter-gate insulating film having an aperture, a fifth and a sixth control gate electrode layer, and a third metallic silicide film; and a liner insulating film directly disposed on a first source and drain region of the memory cell transistor, a second source and drain region of the low voltage transistor, and a third source and drain region of the high voltage transistor. | 07-08-2010 |
20100176433 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a pair of select gate structures which are opposed to each other and which are formed in a select transistor formation area, each of the select gate structures including a gate insulating film formed on a semiconductor substrate and a gate electrode formed on the gate insulating film, and a pair of memory cell gate structure groups which are formed in a pair of memory cell formation areas between which the select transistor formation area is interposed and each of which has a plurality of memory cell gate structures arranged at the same pitch, the pair of select gate structures having sides which are opposed to each other, and at least the upper portion of each of the opposed sides of the select gate structures being inclined. | 07-15-2010 |
20100176435 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREFOR - First gate electrodes of memory cell transistors are formed in series with each other on a semiconductor substrate. A second gate electrode of a first selection transistor is formed adjacent to one end of the first electrodes. A third gate electrode of a second selection transistor is formed adjacent to the second electrode. A fourth gate electrode of a peripheral transistor is formed on the substrate. First, second, and third sidewall films are formed on side surfaces of the second, third, and fourth gate electrodes, respectively. A film thickness of the third sidewall film is larger than that of the first and second sidewall films. A space between the first electrode and the second electrode is larger than a space between the first electrodes, and a space between the second electrode and the third electrode is larger than a space between the first electrode and the second electrode. | 07-15-2010 |
20100214847 | SEMICONDUCTOR STORAGE DEVICE AND READ VOLTAGE CORRECTION METHOD - A semiconductor memory device comprises a semiconductor memory, a corrected voltage storage circuit which stores a corrected voltage produced by correcting a read voltage of the semiconductor memory, and a memory controller which reads the corrected voltage from the corrected voltage storage circuit and performs a read operation of the semiconductor memory using the corrected voltage. | 08-26-2010 |
20100270607 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - It is made possible to provide a memory device that can be made very small in size and have a high capacity while being able to effectively suppress short-channel effects. A nonvolatile semiconductor memory device includes: a first insulating film formed on a semiconductor substrate; a semiconductor layer formed above the semiconductor substrate so that the first insulating film is interposed between the semiconductor layer and the semiconductor substrate; a NAND cell having a plurality of memory cell transistors connected in series, each of the memory cell transistors having a gate insulating film formed on the semiconductor layer, a floating gate formed on the gate insulating film, a second insulating film formed on the floating gate, and a control gate formed on the second insulating film; a source region having an impurity diffusion layer formed in one side of the NAND cell; and a drain region having a metal electrode formed in the other side of the NAND cell. | 10-28-2010 |
20110024827 | NONVOLATILE SEMICONDUCTOR MEMORY - A nonvolatile semiconductor memory according to an aspect of the invention comprises a semiconductor substrate which has an SOI region and an epitaxial region at its surface, a buried oxide film arranged on the semiconductor substrate in the SOI region, an SOI layer arranged on the buried oxide film, a plurality of memory cells arranged on the SOI layer, an epitaxial layer arranged in the epitaxial region, and a select gate transistor arranged on the epitaxial layer, wherein the SOI layer is made of a microcrystalline layer. | 02-03-2011 |
20110069542 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE INCLUDING NAND-TYPE FLASH MEMORY AND THE LIKE - A nonvolatile semiconductor memory device is provided with a memory cell array, a judgment potential correction circuit, and a readout circuit. In the memory cell array, a plurality of memory cells are arranged in a matrix form, and the array includes a first memory cell as a readout object and a second memory cell disposed adjacent to the first memory cell. The judgment potential correction circuit corrects a judgment potential based on a threshold value of the second memory cell. The readout circuit reads the first memory cell as the readout object by use of the corrected judgment potential. | 03-24-2011 |
20110085377 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE, AND METHOD FOR CONTROLLING NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - According to an aspect of the present invention, there is provided, a nonvolatile semiconductor storage device including: a substrate; a stacked portion that includes a plurality of conductor layers and a plurality of insulation layers alternately stacked on the substrate, at least one layer of the plurality of conductor layers and the plurality of insulation layers forming a marker layer; a charge accumulation film that is formed on an inner surface of a memory plug hole that is formed in the stacked portion from a top surface to a bottom surface thereof; and a semiconductor pillar that is formed inside the memory plug hole through the charge accumulation film. | 04-14-2011 |
20110092033 | NONVOLATILE SEMICONDUCTOR MEMORY AND PROCESS OF PRODUCING THE SAME - A nonvolatile semiconductor memory of an aspect of the present invention comprises a semiconductor substrate, a pillar-shaped semiconductor layer extending in the vertical direction with respect to the surface of the semiconductor substrate, a plurality of memory cells arranged in the vertical direction on the side surface of the semiconductor layer and having a charge storage layer and a control gate electrode, a first select gate transistor arranged on the semiconductor layer at an end of the memory cells on the side of the semiconductor substrate, and a second select gate transistor arranged on the semiconductor layer on the other end of the memory cells opposite to the side of the semiconductor substrate, wherein the first select gate transistor includes a diffusion layer in the semiconductor substrate and is electrically connected to the pillar-shaped semiconductor layer by way of the diffusion layer that serves as the drain region. | 04-21-2011 |
20110108905 | NONVOLATILE SEMICONDUCTOR MEMORY - A nonvolatile semiconductor memory includes first and second memory cells having a floating gate and a control gate. The floating gate of the first and second memory cells is comprised a first part, and a second part arranged on the first part, and a width of the second part in an extending direction of the control gate is narrower than that of the first part. A first space between the first parts of the first and second memory cells is filled with one kind of an insulator. The control gate is arranged at a second space between the second parts of the first and second memory cells. | 05-12-2011 |
20110143530 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device according to the present invention includes: a first transistor formed on a semiconductor substrate | 06-16-2011 |
20110233652 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE - A non-volatile semiconductor storage device includes: a memory cell area in which a plurality of electrically rewritable memory cells are formed; and a peripheral circuit area in which transistors that configure peripheral circuits to control the memory cells are formed. The memory cell area has formed therein: a semiconductor layer formed to extend in a vertical direction to a semiconductor substrate; a plurality of conductive layers extending in a parallel direction to, and laminated in a vertical direction to the semiconductor substrate; and a property-varying layer formed between the semiconductor layer and the conductive layers and having properties varying depending on a voltage applied to the conductive layers. The peripheral circuit area has formed therein a plurality of dummy wiring layers that are formed on the same plane as each of the plurality of conductive layers and that are electrically separated from the conductive layers. | 09-29-2011 |
20110249493 | NAND FLASH MEMORY - In a state in which a first and second selection gate transistors are turned off and a first voltage is applied to a control gate of a second memory cell transistor which is connected to a source line side of a first memory cell transistor selected from among the memory cell transistors and which is to be cut off, a second voltage which is higher than the first voltage and which causes a plurality of third memory cell transistors remaining unselected in the memory cell transistors to conduct is applied to control gates of the third memory cell transistors, and thereafter a threshold voltage of the first memory cell transistor is changed to a threshold voltage higher than the first threshold voltage corresponding to the erase state by applying a third voltage which is higher than the second voltage to a control gate of the first memory cell transistor. | 10-13-2011 |
20110250744 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor memory device includes a first block having first memory cells and first select transistors, a second block having second memory cells and second select transistors, and arranged adjacent to the first block in a first direction, the second select transistor being arranged to face the first select transistor and commonly having a diffusion region with the first select transistor, a first interconnection layer provided on the diffusion region between the first and second blocks and extending in a second direction, and a second interconnection layer having a first portion provided in contact with an upper portion of the first interconnection layer and extending to a portion outside the first interconnection layer, and a second portion extending in the second direction and connected to the first portion in a portion outside a portion on the first interconnection layer. | 10-13-2011 |
20110272745 | SEMICONDUCTOR MEMORY AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode. | 11-10-2011 |
20110272755 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device comprising a first insulating film provided on a semiconductor substrate in a cell transistor region, a first conductive film provided on the first insulating film, an inter-electrode insulating film provided on the first conductive film, a second conductive film provided on the inter-electrode insulating film and having a first metallic silicide film on a top surface thereof, first source/drain regions formed on a surface of the semiconductor substrate, a second insulating film provided on the semiconductor substrate in at least one of a selection gate transistor region and a peripheral transistor region, a third conductive film provided on the second insulating film and having a second metallic silicide film having a thickness smaller than a thickness of the first metallic silicide film on a top surface thereof, and a second source/drain regions formed on the surface of the semiconductor substrate. | 11-10-2011 |
20120094461 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREFOR - First gate electrodes of memory cell transistors are formed in series with each other on a semiconductor substrate. A second gate electrode of a first selection transistor is formed adjacent to one end of the first electrodes. A third gate electrode of a second selection transistor is formed adjacent to the second electrode. A fourth gate electrode of a peripheral transistor is formed on the substrate. First, second, and third sidewall films are formed on side surfaces of the second, third, and fourth gate electrodes, respectively. A film thickness of the third sidewall film is larger than that of the first and second sidewall films. A space between the first electrode and the second electrode is larger than a space between the first electrodes, and a space between the second electrode and the third electrode is larger than a space between the first electrode and the second electrode. | 04-19-2012 |
20120181598 | NONVOLATILE SEMICONDUCTOR MEMORY - A nonvolatile semiconductor memory includes first and second memory cells having a floating gate and a control gate. The floating gate of the first and second memory cells is comprised a first part, and a second part arranged on the first part, and a width of the second part in an extending direction of the control gate is narrower than that of the first part. A first space between the first parts of the first and second memory cells is filled with one kind of an insulator. The control gate is arranged at a second space between the second parts of the first and second memory cells. | 07-19-2012 |
20130010541 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes a memory cell which stores data and which is capable of being rewritten electrically, a bit line which is connected electrically to one end of a current path of the memory cell, a control circuit which carries out a verify operation to check a write result after data is written to the memory cell, and a voltage setting circuit which sets a charging voltage for the bit line in a verify operation and a read operation and makes a charging voltage in a read operation higher than a charging voltage in a verify operation. | 01-10-2013 |
20140264227 | SEMICONDUCTOR MEMORY AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode. | 09-18-2014 |