Patent application number | Description | Published |
20090047784 | RESIST STRIPPING METHODS USING BACKFILLING MATERIAL LAYER - A method for fabricating a microelectronic structure provides for forming a backfilling material layer at least laterally adjacent, and preferably laterally adjoining, a resist layer located over a substrate. Preferably, the resist layer comprises a surface treated resist layer. Optionally, the backfilling material layer may be surface treated similarly to the surface treated resist layer. Under such circumstances: (1) surface portions of the backfilling material layer and resist layer; and (2) remaining portions of the backfilling material layer and resist layer, may be sequentially stripped using a two step etch method, such as a two step plasma etch method. Alternatively, a surface portion of the surface treated resist layer only may be stripped while using a first etch method, and the remaining portions of the resist layer and backfilling material layer may be planarized prior to being simultaneously stripped while using a second etch method. | 02-19-2009 |
20110006367 | GATE PATTERNING OF NANO-CHANNEL DEVICES - Methodologies and gate etching processes are presented to enable the fabrication of gate conductors of semiconductor devices, such as NFETs and/or PFETs, which are equipped with nano-channels. In one embodiment, a sacrificial spacer of equivalent thickness to the diameter of the gate nano-channel is employed and is deposited after patterning the gate conductor down to the gate dielectric. The residue gate material that is beneath the nano-channel is removed utilizing a medium to high density, bias-free, fluorine-containing or fluorine- and chlorine-containing isotropic etch process without compromising the integrity of the gate. In another embodiment, an encapsulation/passivation layer is utilized. In yet further embodiment, no sacrificial spacer or encapsulation/passivation layer is used and gate etching is performed in an oxygen and nitrogen-free ambient. | 01-13-2011 |
20120193680 | STRUCTURE WITH ISOTROPIC SILICON RECESS PROFILE IN NANOSCALE DIMENSIONS - A trench is formed by an anisotropic etch in a semiconductor material layer employing a masking layer, which can be gate spacers. In one embodiment, an adsorbed fluorine layer is provided at a cryogenic temperature only on vertical sidewalls of the semiconductor structure including the sidewalls of the trench. The adsorbed fluorine layer removes a controlled amount of the underlying semiconductor material once the temperature is raised above the cryogenic temperature. The trench can be filled with another semiconductor material to generate stress in the semiconductor material layer. In another embodiment, the semiconductor material is laterally etched by a plasma-based etch at a controlled rate while a horizontal portion of a contiguous oxide liner prevents etch of the semiconductor material from the bottom surface of the trench. | 08-02-2012 |
20120193715 | STRUCTURE WITH ISOTROPIC SILICON RECESS PROFILE IN NANOSCALE DIMENSIONS - A trench is formed by an anisotropic etch in a semiconductor material layer employing a masking layer, which can be gate spacers. In one embodiment, an adsorbed fluorine layer is provided at a cryogenic temperature only on vertical sidewalls of the semiconductor structure including the sidewalls of the trench. The adsorbed fluorine layer removes a controlled amount of the underlying semiconductor material once the temperature is raised above the cryogenic temperature. The trench can be filled with another semiconductor material to generate stress in the semiconductor material layer. In another embodiment, the semiconductor material is laterally etched by a plasma-based etch at a controlled rate while a horizontal portion of a contiguous oxide liner prevents etch of the semiconductor material from the bottom surface of the trench. | 08-02-2012 |
20130087860 | BORDERLESS SELF-ALIGNED METAL CONTACT PATTERNING USING PRINTABLE DIELECTRIC MATERIALS - Borderless self-aligned metal contacts to high density complementary metal oxide semiconductor (CMOS) circuits and methods for constructing the same. An example method includes creating an enclosed region for metal deposition defined by the gates of the adjacent transistors and an opposing pair of dielectric walls adjacent to source regions and drain regions of the adjacent transistors. The method further includes depositing a metal layer within the enclosed region. The metal contacts thus formed are self-aligned to the enclosed regions. | 04-11-2013 |
20130123159 | AQUEOUS CERIUM-CONTAINING SOLUTION HAVING AN EXTENDED BATH LIFETIME FOR REMOVING MASK MATERIAL - An aqueous solution of a cerium (IV) complex or salt having an extended lifetime is provided. In one embodiment, the extended lifetime is achieved by adding at least one booster additive to an aqueous solution of the cerium (IV) complex or salt. In another embodiment, the extended lifetime is achieved by providing an aqueous solution of a cerium (IV) complex or salt and a cerium (III) complex or salt. The cerium (III) complex or salt can be added or it can be generated in-situ by introducing a reducing agent into the aqueous solution of the cerium (IV) complex or salt. The aqueous solution can be used to remove a mask material, especially an ion implanted and patterned photoresist, from a surface of a semiconductor substrate. | 05-16-2013 |
20130143397 | USE OF AN ORGANIC PLANARIZING MASK FOR CUTTING A PLURALITY OF GATE LINES - An organic planarizing layer (OPL) is formed atop a semiconductor substrate which includes a plurality of gate lines thereon. Each gate line includes at least a high k gate dielectric and a metal gate. A patterned photoresist having at least one pattern formed therein is then positioned atop the OPL. The at least one pattern in the photoresist is perpendicular to each of the gate lines. The pattern is then transferred by etching into the OPL and portions of each of the underlying gate lines to provide a plurality of gate stacks each including at least a high k gate dielectric portion and a metal gate portion. The patterned photoresist and the remaining OPL layer are then removed utilizing a sequence of steps including first contacting with a first acid, second contacting with an aqueous cerium-containing solution, and third contacting with a second acid. | 06-06-2013 |
20140124870 | SPUTTER AND SURFACE MODIFICATION ETCH PROCESSING FOR METAL PATTERNING IN INTEGRATED CIRCUITS - One embodiment of an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices, wherein at least some of the plurality of conductive lines have pitches of less than one hundred nanometers and sidewall tapers of between approximately eighty and ninety degrees. Another embodiment of an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices, wherein at least some of the plurality of conductive lines are fabricated by providing a layer of conductive metal in a multi-layer structure fabricated upon a wafer and sputter etching the layer of conductive metal using a methanol plasma, wherein a portion of the layer of conductive metal that remains after the sputter etching forms the one or more conductive lines. | 05-08-2014 |
20140124935 | SPUTTER AND SURFACE MODIFICATION ETCH PROCESSING FOR METAL PATTERNING IN INTEGRATED CIRCUITS - One embodiment of an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices, wherein at least some of the plurality of conductive lines have line widths of less than forty nanometers. Another embodiment of an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices, wherein at least some of the plurality of conductive lines are fabricated by providing a layer of conductive metal in a multi-layer structure fabricated upon a wafer, performing a first sputter etch of the layer of conductive metal using a methanol plasma, and performing a second sputter etch of the layer of conductive metal using a second plasma, wherein a portion of the layer of conductive metal that remains after the second sputter etch forms the one or more conductive lines. | 05-08-2014 |
20140127906 | SPUTTER AND SURFACE MODIFICATION ETCH PROCESSING FOR METAL PATTERNING IN INTEGRATED CIRCUITS - Fabricating conductive lines in an integrated circuit includes providing a conductive metal in a multi-layer structure, performing a first sputter etch of the conductive metal using methanol plasma, and performing a second sputter etch of the conductive metal using a second plasma, wherein a portion of the conductive metal that remains after the second sputter etch forms the conductive lines. Alternatively, fabricating conductive lines includes providing a conductive metal as an intermediate layer in a multi-layer structure, etching the multi-layer structure to expose the conductive metal, performing a first etch of the conductive metal using methanol plasma, performing a second sputter etch of the conductive metal using a second plasma, wherein a portion of the conductive metal that remains after the second sputter etch forms the conductive lines, forming a liner that surrounds the conductive lines, and depositing a dielectric layer on the multi-layer structure. | 05-08-2014 |
20150243602 | SPUTTER AND SURFACE MODIFICATION ETCH PROCESSING FOR METAL PATTERNING IN INTEGRATED CIRCUITS - One embodiment of an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices, wherein at least some of the plurality of conductive lines have pitches of less than one hundred nanometers and sidewall tapers of between approximately eighty and ninety degrees. Another embodiment of an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices, wherein at least some of the plurality of conductive lines are fabricated by providing a layer of conductive metal in a multi-layer structure fabricated upon a wafer and sputter etching the layer of conductive metal using a methanol plasma, wherein a portion of the layer of conductive metal that remains after the sputter etching forms the one or more conductive lines. | 08-27-2015 |
Patent application number | Description | Published |
20090200636 | SUB-LITHOGRAPHIC DIMENSIONED AIR GAP FORMATION AND RELATED STRUCTURE - Sub-lithographic dimensioned air gap formation and related structure are disclosed. In one embodiment, a method includes forming a dielectric layer including interconnects on a substrate; depositing a cap layer on the dielectric layer; depositing a photoresist over the cap layer; patterning the photoresist to include a first trench pattern at most partially overlying the interconnects; forming a spacer within the first trench pattern to form a second trench pattern having a sub-lithographic dimension; transferring the second trench pattern into the cap layer and into the dielectric layer between the interconnects; and depositing another dielectric layer to form an air gap by pinching off the trench in the dielectric layer. | 08-13-2009 |
20100252810 | GATE PATTERNING OF NANO-CHANNEL DEVICES - Methodologies and gate etching processes are presented to enable the fabrication of gate conductors of semiconductor devices, such as NFETs and/or PFETs, which are equipped with nano-channels. In one embodiment, a sacrificial spacer of equivalent thickness to the diameter of the gate nano-channel is employed and is deposited after patterning the gate conductor down to the gate dielectric. The residue gate material that is beneath the nano-channel is removed utilizing a medium to high density, bias-free, fluorine-containing or fluorine- and chlorine-containing isotropic etch process without compromising the integrity of the gate. In another embodiment, an encapsulation/passivation layer is utilized. In yet further embodiment, no sacrificial spacer or encapsulation/passivation layer is used and gate etching is performed in an oxygen and nitrogen-free ambient. | 10-07-2010 |
20110303274 | SOLAR CELLS WITH PLATED BACK SIDE SURFACE FIELD AND BACK SIDE ELECTRICAL CONTACT AND METHOD OF FABRICATING SAME - The present disclosure provides a method of forming a back side surface field of a solar cell without utilizing screen printing. The method includes first forming a p-type dopant layer directly on the back side surface of the semiconductor substrate that includes a p/n junction utilizing an electrodeposition method. The p/n junction is defined as the interface that is formed between an n-type semiconductor portion of the substrate and an underlying p-type semiconductor portion of the substrate. The plated structure is then annealed to from a P++ back side surface field layer directly on the back side surface of the semiconductor substrate. Optionally, a metallic film can be electrodeposited on an exposed surface of the P++ back side surface layer. | 12-15-2011 |
20120325312 | SOLAR CELLS WITH PLATED BACK SIDE SURFACE FIELD AND BACK SIDE ELECTRICAL CONTACT AND METHOD OF FABRICATING SAME - The present disclosure provides a method of forming a back side surface field of a solar cell without utilizing screen printing. The method includes first forming a p-type dopant layer directly on the back side surface of the semiconductor substrate that includes a p/n junction utilizing an electrodeposition method. The p/n junction is defined as the interface that is formed between an n-type semiconductor portion of the substrate and an underlying p-type semiconductor portion of the substrate. The plated structure is then annealed to from a P++ back side surface field layer directly on the back side surface of the semiconductor substrate. Optionally, a metallic film can be electrodeposited on an exposed surface of the P++ back side surface layer. | 12-27-2012 |
20130105916 | HIGH SELECTIVITY NITRIDE ETCH PROCESS | 05-02-2013 |
20130105947 | HIGH ASPECT RATIO AND REDUCED UNDERCUT TRENCH ETCH PROCESS FOR A SEMICONDUCTOR SUBSTRATE | 05-02-2013 |
20130105996 | LOW ENERGY ETCH PROCESS FOR NITROGEN-CONTAINING DIELECTRIC LAYER | 05-02-2013 |
20130108833 | HIGH FIDELITY PATTERNING EMPLOYING A FLUOROHYDROCARBON-CONTAINING POLYMER | 05-02-2013 |
20130328173 | HIGH ASPECT RATIO AND REDUCED UNDERCUT TRENCH ETCH PROCESS FOR A SEMICONDUCTOR SUBSTRATE - A hydrofluorocarbon gas is employed as a polymer deposition gas in an anisotropic etch process employing an alternation of an etchant gas and the polymer deposition gas to etch a deep trench in a semiconductor substrate. The hydrofluorocarbon gas can generate a thick carbon-rich and hydrogen-containing polymer on sidewalls of a trench at a thickness on par with the thickness of the polymer on a top surface of the semiconductor substrate. The thick carbon-rich and hydrogen-containing polymer protects sidewalls of a trench, thereby minimizing an undercut below a hard mask without degradation of the overall rate. In some embodiments, an improvement in the overall etch rate can be achieved. | 12-12-2013 |
20140120903 | BASE STATION POWER CONTROL IN A MOBILE NETWORK - The present disclosure relates generally to the field of base station power control in a mobile network. In various examples, base station power control in a mobile network may be implemented in the form of systems, methods and/or algorithms. | 05-01-2014 |
20140120904 | BASE STATION POWER CONTROL IN A MOBILE NETWORK - The present disclosure relates generally to the field of base station power control in a mobile network. In various examples, base station power control in a mobile network may be implemented in the form of systems, methods and/or algorithms. | 05-01-2014 |
20140273437 | SUBTRACTIVE PLASMA ETCHING OF A BLANKET LAYER OF METAL OR METAL ALLOY - A method of forming at least one metal or metal alloy feature in an integrated circuit is provided. In one embodiment, the method includes providing a material stack including at least an etch mask located on a blanker layer of metal or metal alloy. Exposed portions of the blanket layer of metal or metal alloy that are not protected by the etch mask are removed utilizing an etch comprising a plasma that forms a polymeric compound and/or complex which protects a portion of the blanket layer of metal or metal alloy located directly beneath the etch mask during the etch. | 09-18-2014 |
Patent application number | Description | Published |
20080219459 | SYSTEM AND METHOD FOR PROCESSING AUDIO SIGNAL - The present invention provides for methods and systems for digitally processing an audio signal. Specifically the present invention provides for a speaker system that is configured to digitally process an audio signal in a manner such that studio-quality sound that can be reproduced. | 09-11-2008 |
20090062946 | SYSTEM AND METHOD FOR DIGITAL SIGNAL PROCESSING - The present invention provides for methods and systems for digitally processing audio signals by adjusting the gain of a signal a first time, using a digital processing device located between a radio head unit and a speaker. The methods and systems may filter the adjusted signal with a first low shelf filter, compress the filtered signal with a first compressor, process the signal with a graphic equalizer, compress the processed signal with a second compressor and adjust the gain of the compressed signal a second time. The methods and systems may also filter the signal received from the first low shelf filter with a first high shelf filter prior to compressing the filtered signal with the first compressor. The signal may be filtered with a second low shelf filter prior to processing the signal with the graphic equalizer. Some embodiments filter the signal with a second high shelf filter after the signal is filtered with the second low shelf filter. | 03-05-2009 |
20090086996 | SYSTEM AND METHOD FOR PROCESSING AUDIO SIGNAL - The present invention provides for methods and systems for digitally processing an audio signal. Specifically, the present invention provides for a speaker system that is configured to digitally process an audio signal in a manner such that studio-quality sound that can be reproduced. | 04-02-2009 |
20090105858 | SYSTEM AND METHOD FOR DIGITAL SIGNAL PROCESSING - The present invention provides methods and systems for digitally processing audio signals. Some embodiments receive an audio signal and converting it to a digital signal. The gain of the digital signal may be adjusted a first time, using a digital processing device located between a receiver and a driver circuit. The adjusted signal can be filtered with a first low shelf filter. The systems and methods may compress the filtered signal with a first compressor, process the signal with a graphic equalizer, and compress the processed signal with a second compressor. The gain of the compressed signal can be adjusted a second time. These may be done using the digital processing device. The signal may then be output through an amplifier and driver circuit to drive a personal audio listening device. In some embodiments, the systems and methods described herein may be part of the personal audio listening device. | 04-23-2009 |
20130121507 | SYSTEM AND METHOD FOR DIGITAL SIGNAL PROCESSING - The present invention provides methods and systems for digitally processing audio signals. Some embodiments receive an audio signal and converting it to a digital signal. The gain of the digital signal may be adjusted a first time, using a digital processing device located between a receiver and a driver circuit. The adjusted signal can be filtered with a first low shelf filter. The systems and methods may compress the filtered signal with a first compressor, process the signal with a graphic equalizer, and compress the processed signal with a second compressor. The gain of the compressed signal can be adjusted a second time. These may be done using the digital processing device. The signal may then be output through an amplifier and driver circuit to drive a personal audio listening device. In some embodiments, the systems and methods described herein may be part of the personal audio listening device. | 05-16-2013 |
20130148823 | SYSTEM AND METHOD FOR DIGITAL SIGNAL PROCESSING - The present invention provides methods and systems for digitally processing audio signals in broadcasting and/or transmission applications. In particular, the present invention includes a pre-transmission processing module which is structured and configured to generate a partially processed signal. A transmitter is then structured to transmit or broadcast the partially processed signal to a receiver, where the signal is then fed to a post-transmission processing module. The post-transmission processing module is structured and configured to further processes the signal based upon, for example, the listening environment, profile(s), etc. and generate a final output signal. | 06-13-2013 |
20130251175 | SYSTEM AND METHOD FOR DIGITAL SIGNAL PROCESSING - The present invention provides methods and systems for digitally processing audio signals in broadcasting and/or transmission applications. In particular, the present invention includes a pre-transmission processing module which is structured and configured to generate a partially processed signal. A transmitter is then structured to transmit or broadcast the partially processed signal to a receiver, where the signal is then fed to a post-transmission processing module. The post-transmission processing module is structured and configured to further processes the signal based upon, for example, the listening environment, profile(s), etc. and generate a final output signal. | 09-26-2013 |
20140112497 | SYSTEM AND METHOD FOR DIGITAL SIGNAL PROCESSING - The present invention provides for methods and systems for digitally processing an audio signal to reproduce high quality sounds on various materials. In various embodiments, a method comprises filtering the signal with a low shelf filter and/or high shelf filter, passing the signal through a first compressor that, filtering the signal again with a low shelf filter and/or high shelf filter, processing the signal with a graphic equalizer based on a selected material profile, passing the signal through a second compressor, and outputting the signal to a transducer. | 04-24-2014 |
20140177870 | SYSTEM AND METHOD FOR DIGITAL SIGNAL PROCESSING - The present invention provides methods and systems for digitally processing audio signals in broadcasting and/or transmission applications. In particular, the present invention includes a pre-transmission processing module which is structured and configured to generate a partially processed signal. A transmitter is then structured to transmit or broadcast the partially processed signal to a receiver, where the signal is then fed to a post-transmission processing module. The post-transmission processing module is structured and configured to further processes the signal based upon, for example, the listening environment, profile(s), etc. and generate a final output signal. | 06-26-2014 |
20140185829 | IN-LINE SIGNAL PROCESSOR - The present invention provides for a communications cable for processing an input signal. Specifically, the present invention includes a communication cable having an input connector structured to receive an input signal, an audio enhancement module configured to process the input signal using a plurality of processing components in order to create an output signal, and an output connector structured to transmit the output signal. | 07-03-2014 |
20150146099 | IN-LINE SIGNAL PROCESSOR - The present invention provides for a cable which enhances an audio signal between two devices, such as an mp3 player and a speaker system, or a set-top box and home theater system. The cable includes integrated hardware and software elements for processing the signal. In various embodiments the cable may also include a user interface and selectable profiles which adjust the processing scheme for various purposes, such as a profile for environments with high ambient noise, or profiles for certain styles of music. | 05-28-2015 |
Patent application number | Description | Published |
20080262925 | Communication system and method for narrowcasting - A system includes an offer datastores including one or more offers from one or more merchants, a registered card module to register one or more payment cards to be used for a purchase transaction, a transaction matching module to identify the one or more merchants from a collection of purchase transaction data and to match the purchase transaction of the identified one or more merchants with one or more offers in the offer datastore from the identified one or more merchants, and a rewards module to determine an incentive to be applied to the one or more payment cards based on any offer associated with the matched merchant and generate a qualified transaction data to be transmitted to an issuer of the one or more payment cards. | 10-23-2008 |
20110276377 | Communication system and method for narrowcasting - A communication system with client devices in communication with at least one communication network. User data stores are also in communication with the communications network and store user data of users using respective ones of the client devices. Offer data stores also in communication with the communications network store offers from merchants. A narrowcasting engine includes an active data gathering module to collect the user data, and an active learning module to generate a user profile based on the user data. The communication engine selects dynamically offers from the offer data store based on the profile, and communicates the selected offers in the offer data store to the users. | 11-10-2011 |
20140156406 | COMMUNICATION SYSTEM AND METHOD FOR NARROWCASTING - A communication system with client devices in communication with at least one communication network. User data stores are also in communication with the communications network and store user data of users using respective ones of the client devices. Offer data stores also in communication with the communications network store offers from merchants. A narrowcasting engine includes an active data gathering module to collect the user data, and an active learning module to generate a user profile based on the user data. The communication engine selects dynamically offers from the offer data store based on the profile, and communicates the selected offers in the offer data store to the users. | 06-05-2014 |