Patent application number | Description | Published |
20080320272 | PARTITION PRIORITY CONTROLLING SYSTEM AND METHOD - A partition priority controlling apparatus includes a partition ID identifying unit, a partition ID match detecting unit for detecting whether or not a partition to which one of a plurality of system board modules belongs matches partitions to which the other system board modules respectively belong for at least one combination of the system board modules, and an inter-crossbar-unit conflict partition detecting unit for detecting a combination of partitions, which make a conflict between two of a plurality of crossbar units, for at least one combination of the two crossbar units on the basis of the determination result of the partition ID identifying unit, and the detection result of the partition ID match detecting unit. | 12-25-2008 |
20110004740 | DATA TRANSFER APPARATUS, INFORMATION PROCESSING APPARATUS AND METHOD OF SETTING DATA TRANSFER RATE - A method of setting transfer rate for information processing apparatus having a plurality of processing apparatus including a processor outputting data and connected by one or a plurality of data transfer apparatuses for transferring the data outputted from the processor, the method includes obtaining a dividing information indicating a manner of dividing the information processing apparatus into a plurality of partitions including at least one of the plurality of processing apparatuses, and setting a transfer rate of each partition for broadcasting data to all of the processors included in the plurality of processing apparatuses in each partition based on the obtained dividing information. | 01-06-2011 |
20110173494 | Data processing system and data processing method - A data processing system for performing stuck-at control includes system boards that process data, a crossbar unit having control units to control communication between each system board, and a system controller without causing an availability ratio of a computer system to fall. When a control unit fails, the crossbar unit sends, among IDs uniquely attached to each system board, the ID of each system board under the control of the failed control unit to the system controller. The system controller determines to which of partitions that logically divide a system each system board corresponding to the ID received from the crossbar unit belongs and sends a stop command to stop driving of each system board belonging to the determined partition. | 07-14-2011 |
20120233487 | INFORMATION PROCESSING APPARATUS AND TIME-OF-DAY CONTROL METHOD - In an information processing apparatus, a control unit includes a first clock device for providing the time of day. A physical domain includes a second clock device, and implements a logical domain that functions as a virtual information processing apparatus. The control unit controls a first time-of-day difference between the time of day of the first clock device and that of the second clock device. The physical domain controls a second time-of-day difference between the time of day of the second clock device and that of the logical domain. In the information processing apparatus, the time of day on the logical domain is controlled based on the first and second time-of-day differences. | 09-13-2012 |
Patent application number | Description | Published |
20080238449 | Fluid sensor and impedance sensor - A fluid sensor detects property of fluid by dipping the sensor in the fluid. The sensor includes: a semiconductor substrate; and a comb-teeth electrode made of a first diffusion layer and disposed on a first surface of the substrate. Although the comb-teeth electrode is capable of directly contacting the fluid without a protection film, corrosion resistance of the sensor against the fluid is improved. Further, since the sensor has no protection film, the sensor can detect the property accurately. | 10-02-2008 |
20090051052 | Semiconductor device - A semiconductor device includes a molding resin layer and a semiconductor element encapsulated with the molding resin layer. The molding resin layer has an opening. A surface of the semiconductor element is partially exposed outside the molding resin layer through the opening. A groove is located in the surface of the semiconductor element around the opening of the molding resin layer. The groove is filled with the molding resin layer to produce anchor effect that enhances adhesive force of the molding resin layer to the surface of the semiconductor element around the opening. | 02-26-2009 |
20090054784 | Ultrasonic sensor - An ultrasonic sensor for detecting an object includes: a piezoelectric element having a piezoelectric body and first and second electrodes for sandwiching the piezoelectric body; an acoustic matching element having a reception surface, which receives an ultrasonic wave reflected by the object; and a circuit electrically coupled with the piezoelectric element via a wire. The piezoelectric element is embedded in the acoustic matching element so that the acoustic matching element covers at least the first electrode, a part of a sidewall of the piezoelectric element and a part of the wire between the circuit and the piezoelectric element, and the sidewall of the piezoelectric element is adjacent to the first electrode. | 02-26-2009 |
20090095073 | Impedance sensor - An impedance sensor for detecting a mixing ratio of a liquid or a gas includes a substrate, at least a pair of electrodes, and a protective film. The substrate is configured to be disposed in the liquid or the gas. The pair of electrodes is disposed on the substrate. The protective film is disposed on the substrate so as to cover the pair of electrodes. The protective film is made of a material having a relative permittivity greater than or equal to 6. | 04-16-2009 |
20090157345 | Detector device for detecting component density contained in mixture fuel - A detector device of the present invention detects densities of components, such as gasoline and ethanol, contained in mixture fuel even when some water is included in the mixture fuel. The detector device includes a sensor having a pair or electrodes, an electronic device for calculating the densities and a memory device for storing permittivities of pure components including water measured beforehand. Alternating current having two different frequencies f | 06-18-2009 |
Patent application number | Description | Published |
20100014930 | CERMET INSERT AND CUTTING TOOL - One aspect of this titanium carbonitride-based cermet insert has a microstructure including 75 to 90 area % of a hard phase and the balance as a binding phase, wherein the hard phase includes a first hard phase in which a core-having structure includes a TiCN phase and a peripheral portion includes a (Ti,W,Ta/Nb)CN phase, a second hard phase including a (Ti,W,Ta/Nb)CN phase, and a third hard phase including a TiCN phase, and the binding phase contains 18 to 33% of Co, 20 to 35% of Ni, 5% or less of Ti and Ta and/or Nb, and 40 to 60 mass % of W. In another aspect of this cermet insert, a total of an amount of Ti converted as carbonitride, an amount of Ta and/or Nb converted as carbide, and an amount of W converted as carbide is 70 to 95 mass %, an amount of W converted as carbide is 20 to 35 mass %, and Co and Ni are 5 to 30 mass %, this cermet insert has a microstructure including a hard phase containing (Ti,W,Ta/Nb)CN and a binding phase containing, as main components thereof, W and Co and/or Ni, and 40 to 65 mass % of the W is contained in the hard phase. This cutting tool includes a holder and the cermet insert described above held and fixed by the holder. | 01-21-2010 |
Patent application number | Description | Published |
20090015201 | Hybrid Vehicle and Control Method Therefor - An HV-ECU executes refresh-discharging of a battery before the battery is charged from a commercial power source using an AC/DC converter. After the battery is refresh-discharged, the HV-ECU outputs a control signal to the AC/DC converter such that the battery is charged from the commercial power source by the drive of the AC/DC converter. | 01-15-2009 |
20090120700 | CONTROL DEVICE FOR HYBRID VEHICLE - The control device for the hybrid vehicle is mounted on the hybrid vehicle including the engine and the motor generator as the driving source and capable of switching at least two modes, i.e., the infinite variable speed mode and the fixed gear ratio mode. When the speed change is performed from the infinite variable speed mode to the fixed gear ratio mode, the first speed change control to maintain the number of revolutions equal to or larger than the number of engine revolutions at the time of setting the infinite variable speed mode and reduce the engine torque to shift the speed gear in the fixed gear ratio mode is executed. Thereby, when the speed change is performed from the infinite variable speed mode to the fixed gear ratio mode, it becomes possible to appropriately suppress the drivability deterioration caused due to the change of the number of engine revolutions. | 05-14-2009 |
20110178690 | VARIATION ESTIMATING DEVICE OF OBJECT - The variation estimating device of object is preferably used for estimating the variation of the object with respect to the time axis. The first estimating unit estimates the variation of the object behind the actual variation of the object, and the second estimating unit estimates the variation of the object before the actual variation of the object. Then, the correcting unit performs the correction of one of the first estimating unit and the second estimating unit based on the other, so as to calculate the variation of the object, when the object varies. Therefore, it becomes possible to improve the estimation accuracy of the variation of the object. | 07-21-2011 |
20110190970 | POWER GENERATION DEVICE EQUIPPED ON VEHICLE - A structure for controlling an engine is simplified in a power generation device equipped on a vehicle which generates power by a driving force of an engine. An operation unit ( | 08-04-2011 |
Patent application number | Description | Published |
20110198715 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - The semiconductor device of this invention includes a semiconductor substrate having a main surface, and a magnetoresistive element located over the main surface of the semiconductor substrate. Further, it includes a protective layer, a wiring, a first upper electrode, and a second upper electrode. The protective layer is disposed so as to cover the side surface of the magnetoresistive element. The wiring is located over the top of the magnetoresistive element. The first upper electrode substantially the same in dimensions in plan view as the magnetoresistive element is disposed over the magnetoresistive element. The second upper electrode is electrically coupled with the first upper electrode over the first upper electrode, and larger in dimensions in plan view than the first upper electrode. | 08-18-2011 |
20120068282 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - To provide a semiconductor device capable of suppressing a short circuit between an upper conductive element and a lower conductive element which constitute an MRAM, and a manufacturing method of the same. | 03-22-2012 |
20130203187 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - The semiconductor device of this invention includes a semiconductor substrate having a main surface, and a magnetoresistive element located over the main surface of the semiconductor substrate. Further, it includes a protective layer, a wiring, a first upper electrode, and a second upper electrode. The protective layer is disposed so as to cover the side surface of the magnetoresistive element. The wiring is located over the top of the magnetoresistive element. The first upper electrode substantially the same in dimensions in plan view as the magnetoresistive element is disposed over the magnetoresistive element. The second upper electrode is electrically coupled with the first upper electrode over the first upper electrode, and larger in dimensions in plan view than the first upper electrode. | 08-08-2013 |
20130253690 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a method of manufacturing a semiconductor device which allows an operation of the semiconductor device to be stabilized without increasing the area occupied thereby. The control gate electrode of a memory cell transistor is formed, and then the memory gate electrode thereof is formed on a lateral side of the control gate electrode. Then, memory offset spacers are formed over the side walls of the memory gate electrode. Then, the memory source region of the memory cell transistor is formed by ion implantation using the memory gate electrode, the memory offset spacers, and the like as a mask. Then, the memory drain region of the memory cell transistor is formed by ion implantation. Then, in the memory cell transistor, sidewall insulating films are formed. The memory offset spacers disappear through cleaning or the like before the sidewall insulating films are formed. | 09-26-2013 |
Patent application number | Description | Published |
20090039451 | METHOD FOR MANUFACTURING A MAGNETIC MEMORY DEVICE AND MAGNETIC MEMORY DEVICE - A method for manufacturing a magnetic memory device which includes a TMR element, and the method includes: a step of forming a lower wiring layer; a step of forming an interlayer insulating layer on the lower wiring layer; a step of forming an opening in the interlayer insulating layer so that the lower wiring layer is exposed; a step of forming a barrier metal layer so that the interlayer insulating layer and an inner surface of the opening are covered; a step of forming a metal layer on the barrier metal layer so that the opening is embedded; a polishing step of removing the metal layer on the barrier metal layer through polishing using the barrier metal layer as a stopper so that a wiring layer that includes a metal layer being embedded in the opening and the barrier metal layer is formed; and an element fabricating step of fabricating a TMR element on the wiring layer. | 02-12-2009 |
20090075471 | Method of manufacturing semiconductor memory device - A nonvolatile semiconductor memory device includes a semiconductor substrate, a first floating gate formed on a main surface of the semiconductor substrate, a second floating gate formed on the main surface of the semiconductor substrate, a first control gate formed on the first floating gate, a second control gate formed on the second floating gate, an interlayer insulating film, and a gap formed in the interlayer insulating film in at least a portion located between the first and second floating gates. Accordingly, a nonvolatile semiconductor memory device for which variations in threshold voltage of a memory cell can be suppressed and an appropriate read operation can be carried out, as well as a method of manufacturing the nonvolatile semiconductor memory device are provided. Further, a capacitance formed between interconnect lines can be reduced and the drive speed can be improved. | 03-19-2009 |
20110121419 | METHOD FOR MANUFACTURING A MAGNETIC MEMORY DEVICE AND MAGNETIC MEMORY DEVICE - A method for manufacturing a magnetic memory device which includes a TMR element, and the method includes: a step of forming a lower wiring layer; a step of forming an interlayer insulating layer on the lower wiring layer; a step of forming an opening in the interlayer insulating layer so that the lower wiring layer is exposed; a step of forming a barrier metal layer so that the interlayer insulating layer and an inner surface of the opening are covered; a step of forming a metal layer on the barrier metal layer so that the opening is embedded; a polishing step of removing the metal layer on the barrier metal layer through polishing using the barrier metal layer as a stopper so that a wiring layer that includes a metal layer being embedded in the opening and the barrier metal layer is formed; and an element fabricating step of fabricating a TMR element on the wiring layer. | 05-26-2011 |
Patent application number | Description | Published |
20100084701 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - A semiconductor device having a nonvolatile memory is reduced in size. In an AND type flash memory having a plurality of nonvolatile memory cells having a plurality of first electrodes, a plurality of word lines crossing therewith, and a plurality of floating gate electrodes disposed at positions which respectively lie between the plurality of adjacent first electrodes and overlap the plurality of word lines, as seen in plan view, the plurality of floating gate electrodes are formed in a convex shape, as seen in cross section, so as to be higher than the first electrodes. As a result, even when nonvolatile memory cells are reduced in size, it is possible to process the floating gate electrodes with ease. In addition, it is possible to improve the coupling ratio between floating gate electrodes and control gate electrodes of the word lines without increasing the area occupied by the nonvolatile memory cells. | 04-08-2010 |
20110284945 | Semiconductor Device and a Method of Manufacturing the Same - A semiconductor device having a nonvolatile memory is reduced in size. In an AND type flash memory having a plurality of nonvolatile memory cells having a plurality of first electrodes, a plurality of word lines crossing therewith, and a plurality of floating gate electrodes disposed at positions which respectively lie between the plurality of adjacent first electrodes and overlap the plurality of word lines, as seen in plan view, the plurality of floating gate electrodes are formed in a convex shape, as seen in cross section, so as to be higher than the first electrodes. As a result, even when nonvolatile memory cells are reduced in size, it is possible to process the floating gate electrodes with ease. In addition, it is possible to improve the coupling ratio between floating gate electrodes and control gate electrodes of the word lines without increasing the area occupied by the nonvolatile memory cells. | 11-24-2011 |
20130307048 | Semiconductor Device and a Method of Manufacturing the Same - A semiconductor device having a nonvolatile memory is reduced in size. In an AND type flash memory having a plurality of nonvolatile memory cells having a plurality of first electrodes, a plurality of word lines crossing therewith, and a plurality of floating gate electrodes disposed at positions which respectively lie between the plurality of adjacent first electrodes and overlap the plurality of word lines, as seen in plan view, the plurality of floating gate electrodes are formed in a convex shape, as seen in cross section, so as to be higher than the first electrodes. As a result, even when nonvolatile memory cells are reduced in size, it is possible to process the floating gate electrodes with ease. In addition, it is possible to improve the coupling ratio between floating gate electrodes and control gate electrodes of the word lines without increasing the area occupied by the nonvolatile memory cells. | 11-21-2013 |
20150072514 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device having a non-volatile memory cell includes forming first insulating films with first conductive films arranged therebetween, recessing the first insulating films using the first conductive films as a mask, so that heights of top surfaces of the first insulating films are lower than heights of top surfaces of the first conductive films, forming a second insulating film over the first conductive and insulating films, forming a second conductive film over the second insulating film, and patterning the first and second conductive films, and the second insulating film. A length of the floating gate in a second direction is larger than a maximum length of the floating gate in a first direction, and a length from a top surface of the second insulating film to a top surface of the floating gate is larger than a length of a space between a plurality the floating gates. | 03-12-2015 |
Patent application number | Description | Published |
20090129715 | Bearing Unit for Driving Wheels - A process for assembling to a knuckle member a bearing unit for driving wheels including a hub, a bearing, and a constant velocity universal joint is simplified. In order to achieve this, a hub ( | 05-21-2009 |
20090162134 | Constant velocity universal joint - The present invention firmly connects an inner joint component and a shaft of a constant velocity universal joint, making it difficult for backlash to occur. An axis hole inner diameter | 06-25-2009 |
20100021102 | WHEEL BEARING DEVICE - The present invention provides a wheel bearing device that can suppress backlash in the circumferential direction and has excellent workability in connecting a hub wheel and a outer joint component of a constant velocity universal joint. The wheel bearing device according to the present invention is that in which a stem shaft | 01-28-2010 |
20100092122 | BEARING DEVICE FOR DRIVING WHEEL, AND ITS ASSEMBLING METHOD - Provided is a small-sized, lightweight, low-cost, and highly reliable bearing device for a driving wheel which needs no tapered spline, and eliminates a circumferential backlash in spline fitting portions to thereby prevent unusual noise. The bearing device for a driving wheel comprises an outer race ( | 04-15-2010 |
20100119186 | Bearing unit for wheel - A cylindrical pilot portion | 05-13-2010 |
Patent application number | Description | Published |
20140067900 | STREAM PROCESSING DEVICE, SERVER, AND STREAM PROCESSING METHOD - A stream processing device executes query processing with respect to data included in a packet input from a network with a duplication unit that duplicates the input packet into a plurality of packets, a protocol processing unit that executes protocol processing corresponding to the network with respect to one packet among the duplicated packets to determine whether or not an error is present, a storage unit that stores a management flag indicating a result of the protocol processing, a data extraction unit that extracts data necessary for the query processing from another packet among the duplicated packets, a query processing unit that executes the query processing with respect to the extracted data, and outputs data including a result of the query processing. An output control unit determines whether to output the data output from the query processing unit from the stream processing device on the basis of the management flag. | 03-06-2014 |
20140250286 | COMPUTER AND MEMORY MANAGEMENT METHOD - A computer comprising: a processor; a memory; and an I/O device, the memory including at least one first memory element and at least one second memory element, wherein a memory area provided by the at least one second memory element includes a data storage area and a data compression area, wherein the computer comprises a virtualization management unit, and wherein the virtualization management unit is configured to: set a working set for storing data required for processing performed by a virtual machine in generating the virtual machine, and control data stored in the working set in such a manner that part of the data stored in the working set is stored in the data compression area based on a state of accesses to the data stored in the working set. | 09-04-2014 |
20160092351 | MEMORY MODULE HAVING DIFFERENT TYPES OF MEMORY MOUNTED TOGETHER THEREON, AND INFORMATION PROCESSING DEVICE HAVING MEMORY MODULE MOUNTED THEREIN - A memory module having different types of memory mounted together on a double-sided substrate has a first edge and opposite second edge and includes a plurality of memory controllers, a plurality of flash memories, and a plurality of second memories having a higher signal transmission rate than the flash memories. A socket terminal for connecting the double-sided substrate to a motherboard is formed on the front surface and the back surface of the double-sided substrate on the first edge side; the memory controllers are disposed on the second edge side; the second memories are disposed on the second edge side at positions opposite the positions at which the memory controllers are disposed; and the flash memories are disposed on at least the back surface thereof at positions that are closer to the first edge than are the positions at which the memory controllers and the second memories are disposed. | 03-31-2016 |
Patent application number | Description | Published |
20140359063 | COMPUTER SYSTEM, CACHE CONTROL METHOD, AND SERVER - A computer system, comprising: a server on which an application providing a service runs; and a storage system for storing data, the server including a cache device in which a server cache for temporarily storing data is set up, and an operating system for controlling the server, the operating system including a cache driver for controlling the server cache, wherein the operating system is configured to hold access information storing a frequency of reading data and a frequency of writing data, and wherein the cache driver is configured to: update the access information in a case where an I/O request; analyze access characteristics of data that is a target for the I/O request based on the access information; and determine whether to store the data that is the target for the I/O request in the server cache. | 12-04-2014 |
20140359227 | COMPUTER SYSTEM AND CACHE CONTROL METHOD - A computer system, comprising: a server; and a storage system, the server including an operating system, the storage system including a storage control part, wherein the operating system is configured to: transmit a read request for first data to the storage system in a case of receiving the read request for the first data not stored in a server cache from an application; store the first data received from the storage system into the server cache, and wherein the storage control part is configured to: read the first data from the storage cache, transmit the read first data to the server, and invalidate the first data stored in the storage cache. | 12-04-2014 |
20150032965 | COMPUTER SYSTEM, CACHE MANAGEMENT METHOD, AND COMPUTER - A computer system, comprising a server on which an application runs, and a storage system that stores data to be used by the application, the cache driver being configured to change, in a case of the condition of a cache area is a first cache condition in which data is readable from a cache area and writing of data into the cache area is prohibited, the condition of the cache area to a third cache condition in which reading of data from the cache area is prohibited and writing of data into the cache area is prohibited, from the first cache condition. | 01-29-2015 |
20150100663 | COMPUTER SYSTEM, CACHE MANAGEMENT METHOD, AND COMPUTER - A computer system comprising: a server on which an application operates; and a storage system that stores data used by the application, the server including an operating system for controlling the server, the operating system including a cache driver for controlling a cache, the cache driver storing access management information for managing the number of accesses to a partial storage area of a volume provided by the storage system, and the cache driver being configured to: manage the number of accesses to the partial storage area of the volume by using the first access management information; replace the storage area to which the number of accesses is to be managed based on a predetermined replacement algorithm; and control arrangement of data in the server cache based on the first access management information. | 04-09-2015 |
20150120859 | COMPUTER SYSTEM, AND ARRANGEMENT OF DATA CONTROL METHOD - A computer system include a service server, a storage server and a management server, wherein the service server includes a operating system, wherein the operating system includes a cache driver, wherein the storage server manages a plurality of tiered storage areas each having an access performance different from one another, wherein the management server includes an alert setting information generation part for generating alert setting information for the service servers to transmit alert information notifying a trigger to change an arrangement of data in accordance with a state of the service, and a control information generation part for generating cache control information including a first command for controlling an arrangement of cache data on a storage cache and tier control information including a second command for controlling an arrangement of the data on the plurality of tiered storage areas. | 04-30-2015 |
20150347032 | DRAM HAVING SDRAM INTERFACE AND FLASH MEMORY CONSOLIDATED MEMORY MODULE - In methods connecting a memory module configured from DRAM, which is high-speed memory, and a memory module configured from flash memory which is slower than DRAM but is high-capacity memory, to a CPU memory bus, in the case of sequential reading, the busy rate of the CPU memory bus increases, and performance degradation occurs easily. In the present invention, an information processing device has a CPU, a CPU memory bus, and a primary storage device. The primary storage device has a first memory module and a second memory module. The first memory module has high-speed memory. The second memory module has memory having the same memory interface as that of the high-speed memory, high-capacity memory having a different memory interface from that of the high-speed memory, and a controller that controls same. The first memory module and second memory module are caused to be accessed by the memory interface of the high-speed memory. | 12-03-2015 |
20150355846 | DRAM with SDRAM Interface, and Hybrid Flash Memory Module - When DRAMs that are high-speed memories and flash memories that are lower in speed but can be larger in capacity than the DRAM are to be mounted on a DIMM, what matters in maximizing CPU memory bus throughput is the arrangement of the mounted components. The present disclosure provides a memory module (DIMM) that includes memory controllers arranged on the module surface closer to a socket terminal and DRAMs serving as high-speed memories arranged on the back surface. Nonvolatile memories as large-capacity memories are arranged on the side farther from the socket terminal. | 12-10-2015 |