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Fujita, Yokohama-Shi
Hayato Fujita, Yokohama-Shi JP
| Patent application number | Description | Published |
|---|---|---|
| 20110268454 | LD DRIVER WITH AN IMPROVED FALLING EDGE OF DRIVING SIGNAL AND OPTICAL TRANSMITTER PROVIDING THE SAME - An LD driver to generate an asymmetrical driving current with a relatively faster falling edge and an optical transmitter having the LD driver are disclosed. The LD driver includes a primary driver and the sub-driver connected in parallel to the primary driver. The primary driver converts the input signal or the delayed signal delayed from the input signal into the primary current. The sub-driver generates a symmetrical current tracing the input or the delayed signal, and an asymmetrical current formed by the OR operation between the input and delayed signals. The driving current is formed by adding the primary current, the symmetrical current and the asymmetrical current. | 11-03-2011 |
Masanori Fujita, Yokohama-Shi JP
| Patent application number | Description | Published |
|---|---|---|
| 20090293105 | ACCESS CONTROL SYSTEM AND ACCESS CONTROL METHOD - An access control system and method is disclosed. The access control system and method includes a terminal and a server. The terminal determines whether to allow access to a requested website and generates a request to the server to download information from the requested website if the terminal determines to allow access. The server determines whether to allow the terminal access to the requested website and provides information from the requested website to the terminal. The server examines the request to determine whether or not the terminal has made a determination whether to allow access to the requested website. The terminal and server work in combination to determine whether to grant access to the requested website. And the server's determination whether to allow the terminal access is dependent on the server's determination of whether or not the terminal has made a determination whether to allow access to the requested website. | 11-26-2009 |
| 20090305686 | MOBILE UNIT, CALL ORIGINATION CONTROLLING METHOD, AND CALL TERMINATION CONTROLLING METHOD - A mobile unit | 12-10-2009 |
Naohisa Fujita, Yokohama-Shi JP
| Patent application number | Description | Published |
|---|---|---|
| 20120076513 | CONVEYING APPARATUS AND IMAGE FORMING APPARATUS - A conveying apparatus or an image forming apparatus includes: a housing including an opening and closing member that can be opened and closed; a conveying path that conveys an object to be conveyed, at least a part of the conveying path being provided adjacent to an inner side of the opening and closing member; a first detector that detects whether the object is present in a predetermined region and outputs a detection signal corresponding to a result of the detection; and an interlocking mechanism that causes, when the opening and closing member is opened, the first detector to change at least one of a position and a structure of the first detector in mechanically association with movement of opening of the opening and closing member, and to output a detection signal which is the same as a detection signal output when the object is present in the predetermined region. | 03-29-2012 |
Naoko Fujita, Yokohama-Shi JP
| Patent application number | Description | Published |
|---|---|---|
| 20120024777 | INORGANIC POROUS SUPPORT-ZEOLITE MEMBRANE COMPOSITE, PRODUCTION METHOD THEREOF, AND SEPARATION METHOD USING THE COMPOSITE - An object of the present invention is to provide a zeolite membrane composite satisfying both the treating amount and the separation performance at a practically sufficient level, which can be applied even in the presence of an organic material and can separate/concentrate an organic material-containing gas or liquid mixture and which is economic without requiring a high energy cost and is not limited in its application range; a production method thereof; and a separation or concentration method using the same. The present invention is an inorganic porous support-zeolite membrane composite, wherein the inorganic porous support contains a ceramic sintered body and the inorganic porous support-zeolite membrane composite has, as a zeolite membrane, a CHA-type zeolite crystal layer on the inorganic porous support surface. | 02-02-2012 |
Norihiro Fujita, Yokohama-Shi JP
| Patent application number | Description | Published |
|---|---|---|
| 20090080261 | NONVOLATILE SEMICONDUCTOR MEMORY - A nonvolatile semiconductor memory, has a first wire; a second wire adjacent to the first wire; a third wire disposed next to the second wire such that the second wire is disposed between the first wire and the third wire; a power supply circuit for setting each of the wires at a predetermined potential; and a determining circuit for determining presence or absence of a short circuit between the wires. | 03-26-2009 |
| 20090103368 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell array and a sense amp circuit. The memory cell array includes bit lines connected to memory cells operative to store first logic data and second logic data smaller in cell current than the first logic. The sense amp circuit has a clamp transistor operative to clamp a bit line voltage. The sense amp circuit is operative to detect data in a selected memory cell via the clamp transistor and the bit line. The sense amp circuit is operative to read data from the selected memory cell in at least the two of first and second read cycles while a control voltage is applied to a gate of the clamp transistor. Different control voltages are applied to the gate of the clamp transistor in the first and second read cycles. | 04-23-2009 |
| 20090109753 | NONVOLATILE SEMICONDUCTOR MEMORY - A semiconductor memory device including: a package; a first semiconductor chip provided in the package; a first nonvolatile memory provided on the first semiconductor chip; a second semiconductor chip provided in the package; a second nonvolatile memory provided on the second semiconductor chip; a system bus provided in the package, the system bus connecting the first and second nonvolatile memories; a plurality of data terminals exposed to outside of the package, the data terminals being connected to the first and second nonvolatile memories through the system bus; and an enable terminal exposed to the outside of the package, the enable terminal being connected to the first and second nonvolatile memories. | 04-30-2009 |
| 20090323432 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes a memory cell which stores data and which is capable of being rewritten electrically, a bit line which is connected electrically to one end of a current path of the memory cell, a control circuit which carries out a verify operation to check a write result after data is written to the memory cell, and a voltage setting circuit which sets a charging voltage for the bit line in a verify operation and a read operation and makes a charging voltage in a read operation higher than a charging voltage in a verify operation. | 12-31-2009 |
| 20100165744 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell array and a sense amp circuit. The memory cell array includes bit lines connected to memory cells operative to store first logic data and second logic data smaller in cell current than the first logic. The sense amp circuit has a clamp transistor operative to clamp a bit line voltage. The sense amp circuit is operative to detect data in a selected memory cell via the clamp transistor and the bit line. The sense amp circuit is operative to read data from the selected memory cell in at least the two of first and second read cycles while a control voltage is applied to a gate of the clamp transistor. Different control voltages are applied to the gate of the clamp transistor in the first and second read cycles. | 07-01-2010 |
| 20100238727 | NONVOLATILE SEMICONDUCTOR MEMORY - A nonvolatile semiconductor memory includes: a first semiconductor chip on which a first memory in mounted; a second semiconductor chip on which a second memory is mounted; wherein in the second memory which is a destination for copying, a read enable operation is performed after booting up a command which makes the read enable operation recognize as a write enable operation, and a data of the first memory, which is a source of the copy, is copied to the second memory. | 09-23-2010 |
| 20110038206 | SEMICONDUCTOR STORAGE DEVICE TO CORRECT THRESHOLD DISTRIBUTION OF MEMORY CELLS BY REWRITING AND METHOD OF CONTROLLING THE SAME - According to one embodiment, a semiconductor storage device includes a first cell, a second cell, a bit line, a first buffer, a second buffer, and a controller. The bit line transfers the data to the first cell and the second cell. The first buffer holds write data to the first cell and the second cell. The second buffer holds read data from the first cell. The controller controls first writing and rewriting executed for the first cell and second writing executed for the second cell. The write data in the first buffer is updated each time a second write signal is given. The controller executes the first writing based on the write data held by the first buffer. The controller performs the second writing based on the write data updated in the first buffer. The controller executes the rewriting based on the read data held by the second buffer. | 02-17-2011 |
Seiji Fujita, Yokohama-Shi JP
| Patent application number | Description | Published |
|---|---|---|
| 20120075003 | ELECTRONIC CIRCUIT - An electronic circuit includes: first through third transistors having a control terminal, first and second terminals; a first direct current path supplying a direct current having passed through between the first terminal and the second terminal of at least one of the second transistor and the third transistor to the second terminal of the transistor at former position compared to the transistor through which the direct current passed; a second direct current path that is different from the first direct current path and supplies a direct current having passed through between the first terminal and the second terminal of at least one of the second transistor and the third transistor to the second terminal of the transistor at former position compared to the transistor through which the direct current passed; and a common coupling point coupling the first direct current path and the second direct current path in common. | 03-29-2012 |
Tadanobu Fujita, Yokohama-Shi JP
| Patent application number | Description | Published |
|---|---|---|
| 20090059289 | DISPLAY SYSTEM, DISPLAY METHOD, AND STORAGE MEDIUM STORING DISPLAY PROGRAM - A display system configured to display a print preview of a roll paper image and a print area includes an acquisition unit configured to acquire a roll paper width, and a horizontal length of a set paper size, a print-area determination unit for determining a print area based on the acquired roll paper width and horizontal length, a determination unit configured to determine whether the determined print area is displayable in a preview area, a calculation unit configured to calculate a scaling required to display the entire print area in a preview according to a vertical length of the print area, and a display control unit configured to, if it is determined by the determination unit that the entire print area is not displayable, preview a roll paper image and a print area based on the scaling calculated by the calculation unit. | 03-05-2009 |
| 20090168081 | PRINTING SYSTEM, PRINTING APPARATUS, AND PREVIEW METHOD FOR PRINTING SYSTEM - A printing system configured to set a segment unit size serving as a unit of a display area for displaying, as images, a list of pages which form the document; acquire a width and a height of each page image from the document data; calculate, when a value of a ratio of the width and the height of the page acquired in the acquiring exceeds a predetermined value, a display area size having a display region larger than the segment unit size; determine, for a page having the value of the ratio exceeding the predetermined value, an enlargement/reduction ratio so as to fit the page into the display area size; and display, a list of pages which form the document, by enlarging or reducing the page based on the enlargement/reduction ratio determined in the determining and displaying the page in a display screen at the display area. | 07-02-2009 |
| 20100231960 | PRINT CONTROL APPARATUS AND METHOD - When a printer apparatus is allowed to execute a printing of a document using paper based on a print setting set by the user, the following processes are executed in order to allow the user to recognize a paper saving print setting. Whether or not there is a print setting which can save an amount of paper compared to the print setting set by the user is determined. If it is determined that a paper saving print setting exists, the user is notified of such a paper saving print setting. | 09-16-2010 |
| 20100245852 | APPLICATION FUNCTION EXTENSION METHOD, SYSTEM, AND PROGRAM - According to an embodiment of the present invention, in a plug-in of a general use application, sheet size information and margin information set by the application are calculated by using a scaling factor at the time of an expansion or reduction printing. The calculated sheet size information and margin information are reconfigured into the application. | 09-30-2010 |
Takafumi Fujita, Yokohama-Shi JP
| Patent application number | Description | Published |
|---|---|---|
| 20090285137 | WIRELESS TRANSMITTING APPARATUS, WIRELESS RECEIVING APPARATUS, WIRELESS TRANSMISSION METHOD, WIRELESS RECEPTION METHOD, WIRELESS COMMUNICATION SYSTEMS, AND WIRELESS COMMUNICATION METHOD - A wireless transmitting apparatus inserts a training signal into a transmission burst at fixed symbol intervals as a pilot signal, a wireless receiving apparatus performs AD conversion of a received burst signal, performs symbol timing recovery, performs frame position detection and pilot signal extraction from the received burst signal for which symbol timing was established, performs frame synchronization, and performs a carrier frequency estimation using pilot signal. A carrier frequency estimation is also performed with respect to a received burst signal for which frame synchronization was established, and channel distortion is estimated and output based on a frequency-corrected received burst signal. Channel distortion estimation is then performed with respect to a frequency-corrected received burst signal, and a data symbol sequence of the channel-compensated received burst signal is converted to a received data bit stream. | 11-19-2009 |
Terunori Fujita, Yokohama-Shi JP
| Patent application number | Description | Published |
|---|---|---|
| 20100022805 | PROCESS FOR PREPARING ALKYLATED AROMATIC COMPOUND - The present invention provides a process in which a ketone is directly reacted with an aromatic compound in a single reaction step to obtain the corresponding alkylated aromatic compound in a higher yield. By reacting an aromatic compound with a ketone and hydrogen in the presence of a solid acid substance and a catalyst composition containing Cu and Zn in a ratio of Zn to Cu ranging from 0.70 to 1.60 (atomic ratio), the corresponding alkylated aromatic compound is prepared. | 01-28-2010 |
| 20100022812 | PROCESS FOR PRODUCING ALKYLATED AROMATIC COMPOUND AND PROCESS FOR PRODUCING PHENOL - The present invention provides an industrially practical process where a ketone and an aromatic compound are directly reacted to obtain a corresponding alkylated aromatic compound in a single reaction step. The process for producing an alkylated aromatic compound is characterized in that it comprises reacting an aromatic compound, a ketone and hydrogen in the presence of a solid acid substance and a catalyst composition comprising at least one metal selected from the group consisting of Co, Re, Ni and a platinum group metal. | 01-28-2010 |
| 20100267908 | Catalyst for olefin polymerization, process for producing olefin polymer, olefin copolymer, novel transition metal compound, and process for producing transition metal compound - [Task] To provide a catalyst for olefin polymerization having an excellent olefin polymerization performance and capable of producing a polyolefin with excellent properties. | 10-21-2010 |
Toshiki Fujita, Yokohama-Shi JP
| Patent application number | Description | Published |
|---|---|---|
| 20100145063 | 2- thioethenyl substituted carbapenem derivatives - 2-Ethenylthio-type carbapenem derivatives of formula (I) or pharmaceutically acceptable salts thereof are provided. The compounds according to the present invention have potent antimicrobial activity and a wide antimicrobial spectrum against pneumococci including penicillin resistant | 06-10-2010 |
Yasuhito Fujita, Yokohama-Shi JP
| Patent application number | Description | Published |
|---|---|---|
| 20120121088 | ENCRYPTION KEY GENERATION DEVICE - A master key (K | 05-17-2012 |
Yumi Fujita, Yokohama-Shi JP
| Patent application number | Description | Published |
|---|---|---|
| 20110033751 | NONAQUEOUS ELECTROLYTE BATTERY, BATTERY PACK AND VEHICLE - A nonaqueous electrolyte battery includes a positive electrode, a negative electrode, a separator and a nonaqueous electrolyte. The negative electrode contains a negative electrode active material having a Lithium ion insertion potential of 0.4 V (vs. Li/Li | 02-10-2011 |