| Patent application number | Description | Published |
|---|
| 20110254070 | TRENCH MOSFET WITH TRENCHED FLOATING GATES IN TERMINATION - A trench MOSFET comprising a plurality of transistor cells, multiple trenched floating gates in termination area is disclosed. The trenched floating gates have trench depth equal to or deeper than body junction depth of body regions in active area. In some preferred embodiments, the trench MOSFET further comprises a gate metal runner surrounding outside the source metal and extending to the gate metal pad. Furthermore, the termination area further comprises an EPR surrounding outside the trenched floating gates. | 10-20-2011 |
| 20110254071 | SHIELDED TRENCH MOSFET WITH MULTIPLE TRENCHED FLOATING GATES AS TERMINATION - A trench MOSFET comprising a plurality of transistor cells having shielded trenched gates and multiple trenched floating gates as termination region is disclosed. The trenched floating gates have trench depth equal to or deeper than body junction depth of body regions in termination area. In some preferred embodiments, the trenched floating gates in the termination area are implemented by using shielded electrode structure. | 10-20-2011 |
| 20110254086 | SHIELDED TRENCH MOSFET WITH MULTIPLE TRENCHED FLOATING GATES AS TERMINATION - A trench MOSFET comprising a plurality of transistor cells having shielded trenched gates and multiple trenched floating gates as termination region is disclosed. The trenched floating gates have trench depth equal to or deeper than body junction depth of body regions in termination area. In some preferred embodiments, the trenched floating gates in the termination area are implemented by using shielded electrode structure. | 10-20-2011 |
| 20110266593 | SEMICONDUCTOR DEVICES WITH GATE-SOURCE ESD DIODE AND GATE-DRAIN CLAMP DIODE - A semiconductor power device integrated with a Gate-Source ESD diode for providing an electrostatic discharge (ESD) protection and a Gate-Drain clamp diode for drain-source avalanche protection. The semiconductor power device further includes a Nitride layer underneath the diodes and a thick oxide layer as an etching stopper layer for protecting a thin oxide layer on top surface of body region from over-etching. | 11-03-2011 |
| 20110284954 | LOW Qgd TRENCH MOSFET INTEGRATED WITH SCHOTTKY RECTIFIER - An integrated circuit includes a plurality of trench MOSFET and a plurality of trench Schottky rectifier. The integrated circuit further comprises: tilt-angle implanted body dopant regions surrounding a lower portion of all trenched gates sidewalls for reducing Qgd; a source dopant region disposed below trench bottoms of all trenched gates for functioning as a current path for preventing a resistance increased caused by the tilt-angle implanted body dopant regions. | 11-24-2011 |
| 20110316075 | TRENCH MOSFET WITH TRENCHED FLOATING GATES HAVING THICK TRENCH BOTTOM OXIDE AS TERMINATION - A power semiconductor power device having composite trench bottom oxide and multiple trench floating gates is disclosed. The gate charge is reduced by forming a pad oxide surrounding a HDP oxide on trench bottom. The multiple trenched floating gates are applied in termination for saving body mask. | 12-29-2011 |
| 20120021580 | METHOD OF MANUFACTURING TRENCH MOSFET STRUCTURES USING THREE MASKS PROCESS - In according with the present invention, a semiconductor device is formed as follows. A contact insulation layer is deposited on the top surface of said silicon layer. A contact mask is applied and following with a dry oxide etching to remove the contact insulation layer from contact open areas. The silicon layer is implanted with a source dopant through the contact open areas and the source dopant is diffused to form source regions, thereby a source mask is saved. A dry silicon etch is carried out to form trenched source-body contacts in the contact open areas, penetrating through the source regions and extending into the body regions. | 01-26-2012 |
| 20120032261 | TRENCH MOSFET HAVING FLOATING DUMMY CELLS FOR AVALANCHE IMPROVEMENT - A trench MOSFET comprising source regions having a doping profile of a Gaussian-distribution along the top surface of epitaxial layer and floating dummy cells formed between edge trench and active area is disclosed. A SBR of n region existing at cell corners renders the parasitic bipolar transistor difficult to turn on, and the floating dummy cells having no parasitic bipolar transistor act as buffer cells to absorb avalanche energy when gate bias is increasing for turning on channel, therefore, the UIS failure issue is avoided and the avalanche capability of the trench MOSFET is enhanced. | 02-09-2012 |
