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Fu, TX
Chong-Cheng Fu, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20100025805 | SEMICONDUCTOR DEVICES WITH EXTENDED ACTIVE REGIONS - A method of making a semiconductor device is achieved in and over a semiconductor layer. A trench is formed adjacent to a first active area. The trench is filled with insulating material. A masking feature is formed over a center portion of the trench to expose a first side of the trench between a first side of the masking feature and the first active area. A step of etching into the first side of the trench leaves a first recess in the trench. A first epitaxial region is grown in the first recess to extend the first active area to include the first recess and thereby form an extended first active region. | 02-04-2010 |
| 20110089581 | SEMICONDUCTOR WAFER HAVING SCRIBE LANE ALIGNMENT MARKS FOR REDUCING CRACK PROPAGATION - A wafer including at least a first die and at least a second die, wherein the first die and the second die are separated from each other by an area located between the first die and the second die, is provided. The wafer further includes an alignment mark group used for aligning the wafer to a tool used for patterning the wafer. The alignment mark group is located entirely within the area between the first die and the second die and the alignment mark group includes a plurality of alignment lines, and wherein each line of the plurality of alignment lines is formed using a plurality of segments separated from each other by a plurality of gaps filled with an insulating material. | 04-21-2011 |
| 20120007155 | SEMICONDUCTOR DEVICES WITH EXTENDED ACTIVE REGIONS - A method of making a semiconductor device is achieved in and over a semiconductor layer. A trench is formed adjacent to a first active area. The trench is filled with insulating material. A masking feature is formed over a center portion of the trench to expose a first side of the trench between a first side of the masking feature and the first active area. A step of etching into the first side of the trench leaves a first recess in the trench. A first epitaxial region is grown in the first recess to extend the first active area to include the first recess and thereby form an extended first active region. | 01-12-2012 |
Dianbo Fu, Plano, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20120063173 | Common Mode Noise Reduction Apparatus and Method - An embodiment common mode noise reduction apparatus comprises a common mode choke, a balance inductor, a first capacitor and a second capacitor. The common mode choke is placed between an input dc source and a primary side network of an isolated power converter. The balance inductor is coupled between an upper terminal of a primary winding of the isolated power converter and a negative terminal of the input dc source. The first capacitor is coupled between the upper terminal of a primary side of a transformer and an upper terminal of a secondary side of the transformer of the isolated power converter. The second capacitor is coupled between a lower terminal of the primary side of the transformer and a lower terminal of the secondary side of the transformer of the isolated power converter. | 03-15-2012 |
Lei Fu, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20090065952 | Semiconductor Chip with Crack Stop - Various semiconductor chip crack stops and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a semiconductor substrate that has a first corner defined by a first edge and a second edge. A crack stop is formed in the semiconductor substrate. The crack stop includes a first projection extending to the first edge and a second projection extending to the second edge to fence off a portion of the semiconductor substrate that includes the first corner. | 03-12-2009 |
| 20090302427 | Semiconductor Chip with Reinforcement Structure - Various semiconductor chip reinforcement structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a semiconductor chip to a substrate wherein the semiconductor chip has a first side facing toward but separated from a second of the substrate to define an interface region. An array of electrical interconnects is provided between the semiconductor chip and the substrate positioned in the interface region. A reinforcement structure is coupled to the first side of the semiconductor chip and the second side of the substrate and in the interface region while outside the array of electrical interconnects. An underfill is provided in the interface region. | 12-10-2009 |
| 20100207250 | Semiconductor Chip with Protective Scribe Structure - Apparatus and methods pertaining to die scribe structures are disclosed. In one aspect, a method of manufacturing is provided that includes fabricating an active region of a semiconductor die so that the active region has at least one corner. A scribe structure is fabricated around the active region so that the scribe structure includes at least one fillet. | 08-19-2010 |
| 20110031603 | SEMICONDUCTOR DEVICES HAVING STRESS RELIEF LAYERS AND METHODS FOR FABRICATING THE SAME - Methods are provided for fabricating a semiconductor device. In accordance with an exemplary embodiment, a method comprises the steps of providing a semiconductor die having a conductive terminal, forming an insulating layer overlying the semiconductor die, and forming a cavity in the insulating layer which exposes the conductive terminal. The method also comprises forming a first stress-relief layer in the cavity, forming an interconnecting structure having a first end electrically coupled to the first stress-relief layer, and having a second end, and electrically and physically coupling the second end of the interconnecting structure to a packaging substrate. | 02-10-2011 |
| 20120061853 | SEMICONDUCTOR CHIP DEVICE WITH UNDERFILL - A method of manufacturing is provided that includes placing a removable cover on a surface of a substrate. The substrate includes a first semiconductor chip positioned on the surface. The first semiconductor chip includes a first sidewall. The removable cover includes a second sidewall positioned opposite the first sidewall. A first underfill is placed between the first semiconductor chip and the surface wherein the second sidewall provides a barrier to flow of the first underfill. Various apparatus are also disclosed. | 03-15-2012 |
Minghua Fu, Plano, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20100216405 | System and method for interference reduction in self-optimizing networks - A method for interference management in a self optimizing network includes determining quality of service constraints for a call; mapping the quality of service constraints for the call to a target signal-to-interference noise ratio; and transmitting power control signals for the call based on the target signal-to-interference noise ratio. The utility function can be optimized for each class of calls over the network so as to maximize the total number of calls that can be handled. | 08-26-2010 |
Samuel Fu, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20080228874 | Method and Apparatus for Collocating Application Monitoring Reports with Web Applications - A computer implemented method, apparatus, and computer usable program code to display a Web site with its corresponding monitoring information. A determination is made as to whether a user at a client data processing system is permitted access monitoring information for a Web site. The Web page is retrieved to form a retrieved Web page in response to a request for a Web page from the Web site. Monitoring information is associated with the retrieved Web page from associated monitoring information if the user is permitted to access the monitoring information to form collocated content. The collocated content is sent to the user at the client data processing system. | 09-18-2008 |
Xinping Fu, Houston, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20120100109 | Method for increasing the replication of oncolytic HSVs in highly resistant tumor cells using mTOR pathway and PI3K inhibitors - The present invention is directed to the administration of an HSV derived oncolytic virus and a PI3K/AKT/mTOR pathway inhibitor to treat various types of resistant tumors. Therapy-resistant tumor formation is one of the main causes for treatment failure in the clinic. The treatment methods and compositions disclosed herein sensitize resistant tumors to the treatment of herpes simplex virus (HSV)-based oncolytic virotherapy. Pre or co-treatment of resistant tumor cells with the mTOR inhibitor, rapamycin, or certain PI3K inhibitors, such as LY294002, can efficiently sensitize the tumors to HSV derived oncolytic viruses, whereby the replication and spread of the viruses are dramatically enhanced. | 04-26-2012 |
Zhan Fu, Houston, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20100110525 | ULTRA-WIDE BAND SLOW LIGHT STRUCTURE USING PLASMONIC GRADED GRATING STRUCTURES - A slow light system includes a substrate and a metal layer formed thereon, the metal layer having a graded grating structure formed at a surface thereof, wherein the grating depth of the grating structure is sized such that surface-plasmon polariton dispersion behavior of the grating structure differs at different respective locations along the grating structure. Different wavelengths of incident light waves can be slowed at the respective locations along the grating structure. | 05-06-2010 |
Zhihong Fu, College Station, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20100152485 | SYSTEM AND METHOD FOR CONVERTING BIOMASS - In accordance with the teachings of the present invention, a system and method converting biomass into useful chemicals are provided. In a particular embodiment, the method includes fermenting biomass in one or more fermentors to produce a fermentation broth comprising ammonium carboxylate salts, the fermentors containing an ammonium carbonate or ammonium bicarbonate buffer. The method further includes reacting the ammonium carboxylate salts from the fermentors with a high-molecular-weight amine to produce amine carboxylate salt, and thermally cracking the amine carboxylate salt to produce carboxylic acid. In another embodiment, the ammonium carboxylate salts from the fermentors may be reacted with a low-molecular-weight amine to produce a low-molecular-weight-amine carboxylate salt. The low-molecular-weight amine in the low-molecular-weight-amine carboxylate salt may then be switched with a high-molecular-weight amine to form a high-molecular-weight-amine carboxylate salt, which is then thermally cracked to produce carboxylic acid. | 06-17-2010 |