Patent application number | Description | Published |
20120063173 | Common Mode Noise Reduction Apparatus and Method - An embodiment common mode noise reduction apparatus comprises a common mode choke, a balance inductor, a first capacitor and a second capacitor. The common mode choke is placed between an input dc source and a primary side network of an isolated power converter. The balance inductor is coupled between an upper terminal of a primary winding of the isolated power converter and a negative terminal of the input dc source. The first capacitor is coupled between the upper terminal of a primary side of a transformer and an upper terminal of a secondary side of the transformer of the isolated power converter. The second capacitor is coupled between a lower terminal of the primary side of the transformer and a lower terminal of the secondary side of the transformer of the isolated power converter. | 03-15-2012 |
20130049918 | Common Mode Choke Apparatus and Method - An embodiment integrated common mode choke comprises a magnetic core, a magnetic plate, a first winding coil and a second winding coil. The magnetic plate is inserted within an inner circumference of the magnetic core. The first winding coil and the second winding coil are wound are wound in the same direction through the magnetic core. The integrated common mode choke is equivalent to a common mode choke and a differential mode choke connected in series. The inductance value of the differential mode choke can be changed by adjusting either the gap between the magnetic plate and the magnetic core or the thickness of the magnetic plate. | 02-28-2013 |
20130050879 | High Efficiency Bridgeless PFC Converter and Method - An embodiment bridgeless power factor correction circuit comprises a first boost converter and a second boost converter connected in parallel. A first switch is coupled between the input of the first boost converter and ground. A second switch is coupled between the input of the second boost converter and ground. Both the first switch and the second switch help to reduce the common mode noise of the bridgeless power factor correction circuit. The bridgeless power factor correction circuit further comprises two surge protection diodes coupled between the inputs of two boost converters and the output of the bridgeless power factor correction circuit. | 02-28-2013 |
20130135903 | Hybrid DC/DC Converters and Methods - An embodiment hybrid dc/dc converter comprises a first power source and a low power converter coupled to the first power source. The low power converter generates an output connected in series with the first power source. The hybrid dc/dc converter further comprises a selection network coupled to the first power source and the output of the low power converter and a main unregulated power converter coupled to the selection network. By controlling the voltage across the output of the low power converter, the hybrid dc/dc converter can achieve high efficiency through the unregulated power converter. | 05-30-2013 |
20130265804 | Apparatus for Resonant Converters - A converter comprises a bridge and a resonant tank coupled between the bridge and an isolation transformer. The converter is configured such that the converter operates at a first constant-gain resonant frequency during a normal operation condition wherein a voltage gain of the converter is essentially insensitive to an output load change and the converter operates at a minimum-gain damping frequency during an abnormal operation condition wherein a voltage gain of the converter is approximately equal to zero. | 10-10-2013 |
20130301314 | Multilevel Inverter Device and Method - An embodiment multilevel inverter comprises a first boost apparatus having an input coupled to a positive dc bus and a second boost apparatus having an input coupled to a negative dc bus. The multilevel inverter further comprise a first switch coupled to an input of an L-C filter and the first boost apparatus, a second switch coupled to the input of the L-C filter and the second boost apparatus, a third switch coupled between the positive dc bus and the first switch and a fourth switch coupled between the negative dc bus and the second switch. | 11-14-2013 |
20140152413 | Coupled Inductor Structure - An embodiment apparatus comprises a magnetic core comprising a first side and a second side opposite the first side, a first winding comprising a first portion wound around the first side and a second portion wound around the second side, a second winding comprising a third portion wound around the first side and a fourth portion wound around the second side, wherein the second portion and the fourth portion are coupled to each other. | 06-05-2014 |
20140198536 | Resonant Converters and Methods - A multilevel LLC resonant converter comprises a resonant tank connected in series with a primary side of a transformer, a first switch and a second switch connected in series, wherein a common node of the first switch and the second switch is coupled to a mid-voltage point through a first isolation switch and the resonant bank and a third switch and a fourth switch connected in series, wherein a common node of the third switch and the fourth switch is coupled to the resonant tank. | 07-17-2014 |
20140254203 | Resonant Converters - A resonant tank comprises a resonant inductor coupled to a switching network and a transformer, a resonant capacitor coupled to the switching network and the transformer, a first parallel inductor implemented as a magnetizing inductance and a second parallel inductor implement as a separate inductor, wherein a first inductance of the first parallel inductor is greater than a second inductance of the second parallel inductor. | 09-11-2014 |
20140254208 | Auxiliary Resonant Apparatus for LLC Converters - A resonant tank comprises a series resonant inductor coupled to a switching network and a transformer, a series resonant capacitor coupled to the switching network and the transformer, a first parallel inductor implemented as a magnetizing inductance of the transformer, a second parallel inductor implement as a separate inductor, wherein a first inductance of the first parallel inductor is greater than a second inductance of the second parallel inductor and a switch connected in series with the second parallel inductor. | 09-11-2014 |
20140319919 | Soft Switching Inverter Device and Method - An inverter comprises a first switch coupled to an input of an output filter and a positive dc bus, a second switch coupled to the input of the output filter and a negative dc bus, a first freewheeling apparatus coupled to the first switch, the second switch and ground, a first soft switching network coupled to the first freewheeling apparatus and the first switch, wherein the first soft switching network is configured such that the first switch is of a first zero voltage transition during a turn-on process of the first switch and a second soft switching network coupled to the first freewheeling apparatus and the second switch, wherein the second soft switching network is configured such that the second switch is of a second zero voltage transition during a turn-on process of the second switch. | 10-30-2014 |
20140334199 | Five-Level Power Converter, and Control Method and Control Apparatus for the Same - A five-level power converter and a control method for the same are provided. The five-level power converter includes an inverter and at least a rectifier, where the rectifier includes at least one rectifier control circuit and four capacitors which are divided into two groups, each with two capacitors connected in parallel, where a first end of a first capacitor to a fourth capacitor is grounded; the rectifier control circuit is configured to input a current to a second end of the first capacitor to the fourth capacitor; and a polarity of charges accumulated at the second ends of the first capacitor and the second capacitor is opposite to a polarity of charges accumulated at the second ends of the third capacitor and the fourth capacitor; and the inverter includes a discharge control circuit, and a first inductor unit and a first load connected in series. | 11-13-2014 |
20150085541 | MULTI-LEVEL INVERTER AND POWER SUPPLY SYSTEM - A multi-level inverter includes two N-level inverter units with pulse width modulation waves staggered by a phase of 180 degrees, and N is an integer greater than or equal to 3; a direct current power source module, where an output end thereof is connected to input ends of the two N-level inverter units; a transformer, where the transformer includes a primary side and a secondary side, an inductor of the primary side and an inductor of the secondary side are coupled, and one end of the inductor of the primary side and one end of the inductor of the secondary side are connected to output ends of the two N-level inverter units respectively. The two N-level inverter units are reversely coupled, and the other end of the inductor of the primary side and the other end of the inductor of the secondary side are connected. | 03-26-2015 |
Patent application number | Description | Published |
20090065952 | Semiconductor Chip with Crack Stop - Various semiconductor chip crack stops and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a semiconductor substrate that has a first corner defined by a first edge and a second edge. A crack stop is formed in the semiconductor substrate. The crack stop includes a first projection extending to the first edge and a second projection extending to the second edge to fence off a portion of the semiconductor substrate that includes the first corner. | 03-12-2009 |
20090302427 | Semiconductor Chip with Reinforcement Structure - Various semiconductor chip reinforcement structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a semiconductor chip to a substrate wherein the semiconductor chip has a first side facing toward but separated from a second of the substrate to define an interface region. An array of electrical interconnects is provided between the semiconductor chip and the substrate positioned in the interface region. A reinforcement structure is coupled to the first side of the semiconductor chip and the second side of the substrate and in the interface region while outside the array of electrical interconnects. An underfill is provided in the interface region. | 12-10-2009 |
20100207250 | Semiconductor Chip with Protective Scribe Structure - Apparatus and methods pertaining to die scribe structures are disclosed. In one aspect, a method of manufacturing is provided that includes fabricating an active region of a semiconductor die so that the active region has at least one corner. A scribe structure is fabricated around the active region so that the scribe structure includes at least one fillet. | 08-19-2010 |
20110031603 | SEMICONDUCTOR DEVICES HAVING STRESS RELIEF LAYERS AND METHODS FOR FABRICATING THE SAME - Methods are provided for fabricating a semiconductor device. In accordance with an exemplary embodiment, a method comprises the steps of providing a semiconductor die having a conductive terminal, forming an insulating layer overlying the semiconductor die, and forming a cavity in the insulating layer which exposes the conductive terminal. The method also comprises forming a first stress-relief layer in the cavity, forming an interconnecting structure having a first end electrically coupled to the first stress-relief layer, and having a second end, and electrically and physically coupling the second end of the interconnecting structure to a packaging substrate. | 02-10-2011 |
20120061853 | SEMICONDUCTOR CHIP DEVICE WITH UNDERFILL - A method of manufacturing is provided that includes placing a removable cover on a surface of a substrate. The substrate includes a first semiconductor chip positioned on the surface. The first semiconductor chip includes a first sidewall. The removable cover includes a second sidewall positioned opposite the first sidewall. A first underfill is placed between the first semiconductor chip and the surface wherein the second sidewall provides a barrier to flow of the first underfill. Various apparatus are also disclosed. | 03-15-2012 |
20120193788 | STACKED SEMICONDUCTOR CHIPS PACKAGING - Various methods and apparatus for joining stacked substrates to a circuit board are disclosed. In one aspect, a method of manufacturing is provided that includes coupling plural substrates to form a stack. At least one of the plural substrates is a semiconductor chip. Plural conductive vias are formed in a first of the plural substrates. Each of the plural conductive vias includes a first end positioned in the first substrate and a second end projecting out of the first substrate. | 08-02-2012 |
20130221517 | SEMICONDUCTOR WORKPIECE WITH BACKSIDE METALLIZATION AND METHODS OF DICING THE SAME - Various semiconductor workpieces and methods of dicing the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a channel in a metallization structure on a backside of a semiconductor workpiece. The semiconductor workpiece includes a substrate. The channel is in substantial alignment with a dicing street on a front side of the semiconductor chip. | 08-29-2013 |
20130341785 | SEMICONDUCTOR CHIP WITH EXPANSIVE UNDERBUMP METALLIZATION STRUCTURES - Methods and apparatus to protect fragile dielectric layers in a semiconductor chip are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first polymer layer over a conductor pad of a semiconductor chip where the conductor pad has a first lateral dimension. An underbump metallization structure is formed on the first polymer layer and in ohmic contact with the conductor pad. The underbump metallization structure has a second lateral dimension greater than the first lateral dimension. A second polymer layer is formed on the first polymer layer with a first opening exposing at least a portion of the underbump metallization structure. | 12-26-2013 |
Patent application number | Description | Published |
20100216405 | System and method for interference reduction in self-optimizing networks - A method for interference management in a self optimizing network includes determining quality of service constraints for a call; mapping the quality of service constraints for the call to a target signal-to-interference noise ratio; and transmitting power control signals for the call based on the target signal-to-interference noise ratio. The utility function can be optimized for each class of calls over the network so as to maximize the total number of calls that can be handled. | 08-26-2010 |
20130121427 | SCALED POWER LINE BASED NETWORK - A power line communication network includes a first power line communication sub-network, a second power line communication sub-network, and an isolation filter disposed between first and second power line communication sub-networks. The isolation filter is configured to pass electrical power signals between the first and second power line communication sub-networks, and to block passage of data communication signals from the first power line communication sub-network to the second power line communication sub-network. | 05-16-2013 |
20130188670 | DYNAMIC IMPROVEMENT OF LINK SYMMETRY IN CO-LOCATED PLC AND RF NETWORKS - An electronic communication device comprises a first transceiver capable of a bi-directional communication session on a first communication medium; a second transceiver capable of a bi-directional communication session on a second communication medium; and a control logic coupled to the first transceiver and the second transceiver, wherein the control logic is configured to receive, from the first transceiver, a first signal, and cause, in response to the first signal, data transmitted by the first transceiver on the first communication medium as part of a communication session to be transmitted instead by the second transceiver on the second communication medium while the first transceiver continues to receive data as part of the communication session. | 07-25-2013 |
20130188673 | DYNAMIC MEDIUM SWITCH IN CO-LOCATED PLC AND RF NETWORKS - An electronic communication device comprises a first transceiver capable of a bi-directional communication session on a first communication medium; a second transceiver capable of a bi-directional communication session on a second communication medium; and a control logic coupled to the first transceiver and the second transceiver and capable of implementing a convergence layer, wherein the control logic is configured to receive, from the first transceiver, a first signal; and cause, in response to the first signal, data received and transmitted by the first transceiver on the first communication medium as part of a communication session to be received and transmitted instead by the second transceiver on the second communication medium. | 07-25-2013 |
20150061636 | AUTOMATIC CALIBRATION METHOD FOR ACTIVE AND REACTIVE POWER MEASUREMENT - A system is provided for calibrating a device. The system includes a reference component, a sampling component, a calibration component, a comparing component and a proportional integral component. The reference component provides a reference power signal based on a voltage instruction and a current instruction. The sampling component samples a voltage signal to obtain a sampled voltage value and samples a current signal to obtain a sampled current value. The calibration component generates a calibrated power signal based on the sampled voltage value and the sampled current. The comparing component generates an error signal based on the reference power signal and the calibrated power signal. The proportional integral component and the calibration component are a feedback system that is operable to calibrate the gain of the sampled voltage and the sample current based on the error signal. | 03-05-2015 |
Patent application number | Description | Published |
20120100109 | Method for increasing the replication of oncolytic HSVs in highly resistant tumor cells using mTOR pathway and PI3K inhibitors - The present invention is directed to the administration of an HSV derived oncolytic virus and a PI3K/AKT/mTOR pathway inhibitor to treat various types of resistant tumors. Therapy-resistant tumor formation is one of the main causes for treatment failure in the clinic. The treatment methods and compositions disclosed herein sensitize resistant tumors to the treatment of herpes simplex virus (HSV)-based oncolytic virotherapy. Pre or co-treatment of resistant tumor cells with the mTOR inhibitor, rapamycin, or certain PI3K inhibitors, such as LY294002, can efficiently sensitize the tumors to HSV derived oncolytic viruses, whereby the replication and spread of the viruses are dramatically enhanced. | 04-26-2012 |
20120237481 | Incorporation of the B18R gene to enhance antitumor effect of virotherapy - The present invention relates to a novel composition and method to potentiate the antitumor effect of an oncolytic virus by providing for resistance against a host's innate interferon response. Particularly, a B18R gene is incorporated into an oncolytic virus. During treatment of a host with the modified oncolytic virus, the oncolytic virus retains its phenotype, and the host's innate immune response has a minimal affect on viral replication. | 09-20-2012 |
20120301506 | Oncolytic Virus as an Inducer for Innate Antitumor Immunity - The present invention is directed to the administration of FusOn-H2, an HSV derived oncolytic virus, to treat tumor cells that are resistant to the lytic effect of the virus. Administration of FusOn-H2 induces the patient's innate immune responses to tumor cells via neutrophils, which are able to destroy tumors efficiently when they migrate to the tumor mass. With the induced innate antitumor immunity, FusOn-H2 is effective at eradicating tumors even when it is used at very low doses. | 11-29-2012 |
20140369977 | Targeting Tumor Neovasculature with Modified Chimeric Antigen Receptors - A T cell transduced with a chimeric antigen receptor can be administered to a host to kill cancer cells. The chimeric antigen receptor can include a targeting moiety with a strong binding affinity to α | 12-18-2014 |