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Fu-Chung

Fu-Chung Chang, Rhinebech, NY US

Patent application numberDescriptionPublished
20090190495GENERAL MULTI-LINK INTERFACE FOR NETWORKING ENVIRONMENTS - A method, information processing system, and computer readable medium manage a plurality of network interfaces. A data packet is accepted at a pseudo network interface. The pseudo network interface manages a plurality of underlying physical network interfaces. The pseudo network interface selects selected physical network interface from the plurality of physical network interfaces for outputting the data packet. The data packet is modified to include a hardware address associated with the selected physical network interface in response to the selecting. The data packet that has been modified is forwarded to the physical network interface that has been selected.07-30-2009
20090190581OVERHEAD REDUCTION FOR MULTI-LINK NETWORKING ENVIRONMENTS - A method, computing node, and computer program storage product maintain network routing information. A first node receives a route status request from a second node. A status is stored at the first node indicating that a route from the second node to the first node is valid only in response to receiving the route status request. The first node transmits a route status reply to the second node.07-30-2009
20090193168INTERRUPT MITIGATION ON MULTIPLE NETWORK ADAPTERS - A method, information processing system, and computer readable medium, mitigate processor assignments. A first processor in a plurality of processors is assigned to a first communication port in a plurality of communication ports. An interrupt associated with the first communication port is generated. An assignment of a processor other than the first processor to handle the interrupt is inhibited.07-30-2009

Fu-Chung Hsieh, Tao Yuan TW

Patent application numberDescriptionPublished
20090170575ELECTRONIC DEVICE - An electronic device including a first module, a second module, at least one first spacer, and at least one second spacer is provided. The first module has a carrying surface. The second module is slidably disposed on the carrying surface and has a bottom surface opposite to the carrying surface. The first spacer is fixed on the carrying surface and suitable for being slid on the bottom surface. The second spacer is fixed on the bottom surface and suitable for being slid on the carrying surface. The first spacer and the second spacer are always kept within an overlapping region between the bottom surface and the carrying surface.07-02-2009

Fu-Chung Wu, Taipei City TW

Patent application numberDescriptionPublished
20090189298Bonding pad structure and debug method thereof - The bonding pad structure includes a main bonding pad and a blank path. The blank path crosses through the main bonding pad for dividing the main bonding pad into a first sub-bonding pad and a second sub-bonding pad. The bonding pad structure may further include a solder covered on the blank path and the main bonding pad selectively. The main bonding pad is regarded as a closed circuit when the solder is covered on the blank path and the main bonding pad. The main bonding pad is regarded as a open circuit when the solder is not covered on the blank path and the main bonding pad. A debug method with the bonding pad structure is also disclosed.07-30-2009