| Patent application number | Description | Published |
|---|
| 20100082930 | GPU ASSISTED GARBAGE COLLECTION - A system and method for efficient garbage collection. A general-purpose central processing unit (CPU) sends a garbage collection request and a first log to a special processing unit (SPU). The first log includes an address and a data size of each allocated data object stored in a heap in memory corresponding to the CPU. The SPU has a single instruction multiple data (SIMD) parallel architecture and may be a graphics processing unit (GPU). The SPU efficiently performs operations of a garbage collection algorithm due to its architecture on a local representation of the data objects stored in the memory. The SPU records a list of changes it performs to remove dead data objects and compact live data objects. This list is subsequently sent to the CPU, which performs the included operations. | 04-01-2010 |
| 20100115502 | Post Processing of Dynamically Generated Code - A system and method are disclosed for improving the performance of compiled Java code. Java source code is annotated and then compiled by a Java compiler to produce annotated Java bytecode, which in turn is compiled by a just-in-time (JIT) compiler into annotated native code. The execution of the annotated native code is monitored with a patching agent, which captures the annotated native code as it is being executed. The captured native code is then provided through an application program interface to a dynamic linkage module, which in turn provides the captured native code to a user or to an application plug-in module for modifications. The modifications are saved as a patch. The annotated native code is then re-executed and the modifications to the annotated native code are applied as a patch by the patching agent. | 05-06-2010 |
| 20100306514 | Correlating Instruction Sequences with CPU Performance Events to Improve Software Performance - A system and method are disclosed for correlating instruction sequences. A plurality of instructions is processed to parse a first sequence of instructions comprising a first area of interest. A first instruction sequence pattern is then generated from the first sequence of instructions. Pattern matching operations are performed with the first instruction sequence pattern. A second sequence of instructions are parsed, comprising a second instruction sequence pattern and a second address of interest that is a substantially equivalent match to the first instruction sequence pattern. | 12-02-2010 |
| 20110004866 | COMBINING CLASSES REFERENCED BY IMMUTABLE CLASSES INTO A SINGLE SYNTHETIC CLASS - A system and method for creating synthetic immutable classes. A processor identifies first and second classes, instances of which include first and second data fields, respectively. The first data fields include a data field that references the second class. In response to determining that the first class is immutable and the second class is immutable, the processor constructs a first synthetic immutable class, an instance of which comprises a combination of the first data fields and the second data fields. The processor creates an instance of the first synthetic immutable class in which the first data fields and the second data fields occupy a contiguous region of a memory. In response to determining the first synthetic immutable class does not include an accessor for the second class, the processor combines header fields of the first and second data fields into a single data field in the first synthetic immutable class. | 01-06-2011 |
| Patent application number | Description | Published |
|---|
| 20110038203 | Reduction of Read Disturb Errors in NAND FLASH Memory - Methods and apparatuses for reduction of Read Disturb errors in a NAND FLASH memory system utilizing modified or extra FLASH memory cells. | 02-17-2011 |
| 20110040925 | Method and Apparatus for Addressing Actual or Predicted Failures in a FLASH-Based Storage System - Methods and apparatuses for enhanced protection of data stored in a FLASH memory system involve a controller capable of adapting to the failure of one or more FLASH memory devices in the memory system. The controller stores data in the form of page stripes, each page stripe composed of data pages, and each data page stored in a different FLASH memory device. The controller also detects failure of a FLASH memory device in which a data page of a particular page stripe is stored, reconstructs the data page, and stores the reconstructed data page in a new page stripe, where the number of data pages in the new page stripe is less than the number of data pages in the particular page stripe, and where no page of the new page stripe is stored in a memory location within the failed FLASH memory device. | 02-17-2011 |
| 20110040926 | FLASH-based Memory System With Variable Length Page Stripes Including Data Protection Information - Methods and apparatuses for enhanced protection of data stored in a FLASH memory system involve a controller capable of protecting data using different size page stripes. The controller is configured to store data in FLASH memory devices in the form of page stripes, each page stripe comprising a plurality of pages of information, each page of information being stored in a different FLASH memory chip. The controller stores the data in a manner such that the pages making up each page stripe includes a plurality of data pages and at least one data protection page. In one implementation, the page stripes stored by the controller include a first page stripe having N data pages and one data protection page, and a second page stripe having M data pages and one data protection page, where N is an integer greater than three and M is an integer less than N. | 02-17-2011 |
| 20110040932 | Efficient Reduction of Read Disturb Errors in NAND FLASH Memory - Methods and apparatuses for reduction of Read Disturb errors in a NAND FLASH memory system comprise a controller configured to organize FLASH memory devices into blocks, each block having a plurality of pages, and each page defining an individually addressable physical memory location. The controller is further configured to accumulate a Block READ Count corresponding to the number of times any pages in a first block of pages have been read since the first block was last erased. Once the READ count reaches a predetermined number, the controller responds to subsequent READ requests for pages within the first block by moving data associated with a requested page to a page in a second, different block without moving data associated with other pages in the first block, and modifying a logical-to-physical translation table to associate the moved data with the physical address of the page in the second block. | 02-17-2011 |
| 20110041037 | FLASH-based Memory System with Static or Variable Length Page Stripes including Data Protection Information and Auxiliary Protection Stripes - Methods and apparatuses for enhanced protection of data stored in a FLASH memory system involve a controller capable of protecting data using page stripes and auxiliary protection stripes. The controller stores the data in a manner such that the pages making up each page stripe include a plurality of data pages and at least one data protection page and the pages making up each auxiliary protection stripe include a plurality of data pages and an auxiliary protection page. At least a plurality of data pages are within one page stripe and one auxiliary protection stripe such that each data page is protected both by a data protection page in the page stripe and an auxiliary protection page in the auxiliary protection stripe. | 02-17-2011 |
| 20110087855 | Method and Apparatus for Protecting Data Using Variable Size Page Stripes in a FLASH-Based Storage System - Methods and apparatuses for enhanced protection of data stored in a FLASH memory system involve a controller capable of using variable size page stripes in the memory system. The controller is configured to store data such that each page stripe comprises a plurality of data pages, with each data page in the page stripe being stored in a different FLASH memory chip. The controller is also configured to maintain one or more buffers containing information reflecting blocks of memory within the FLASH memory chips that have been erased and are available for information storage, and to dynamically determine the number of data pages to be included in a page stripe based on the information in the one or more buffers such that a first page stripe and a second page stripe can have different numbers of data pages. | 04-14-2011 |
| 20110109159 | Active Low-Pass Current Filter - An active low-pass current filter apparatus and method reduces conducted emissions above a predefined cutoff frequency at high power levels. The apparatus and method use a bidirectional DC-DC converter to minimize current fluctuations on a power lead that may result in conducted emissions above the predefined cutoff frequency. The bidirectional DC-DC converter absorbs current from the power lead and feeds current to the load lead as needed to compensate for the current fluctuations on the power lead. Power to the DC-DC converter is provided by a separate auxiliary power source. A monitoring circuit compares the voltage level of the auxiliary power source to a reference voltage and compensates for variations in the voltage level of the auxiliary power source without interfering with the suppression of the conducted emissions. | 05-12-2011 |
