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Fried, NY
Brian Fried, Melville, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20100252189 | Method and kit for decorating a pet's collar and/or leash or lead - A method and a kit for decorating a collar and a leash of a pet includes a collar and a leash or lead preferably made of a nylon material, a set of permanent, non toxic and odorless fabric markers of preferably five different colors, a stencil set of preferably images made preferably of paper stock having a sticky non-toxic backing to keep each image in place when applied to the pet's collar or leash (lead). The markers can be used to color each image while in the stencil set before removing a selected colored image to be placed on the pet's collar or leash for decorating the collar or leash. | 10-07-2010 |
Brian A. Fried, Melville, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20080223748 | Rotating Egg Container - A rotating egg container is disclosed having a body and an internal rotating unit for storing a plurality of eggs. The internal rotating unit has a plurality of egg holding sections joined to two opposing tracks defining a pathway through which the egg holding sections can be moved. | 09-18-2008 |
| 20080237229 | Telescoping Egg Container - A telescoping egg container is disclosed comprising a plurality of slidable egg holder units that can nest one within another, such that the telescoping egg container can be extended or collapsed to accommodate various numbers of eggs to be stored. | 10-02-2008 |
| 20100050394 | Releasable Pull Tie - A pull tie is described comprising an elastomeric cord and a slidable stop. The pull tie can be suitable for releasable, multi-use closures for flexible bags and containers. | 03-04-2010 |
David M. Fried, Ithaca, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20090134463 | SEMICONDUCTOR STRUCTURE AND SYSTEM FOR FABRICATING AN INTEGRATED CIRCUIT CHIP - A semiconductor structure and a system for fabricating an integrated circuit chip. The semiconductor structure includes: a buried oxide layer on a semiconductor wafer; a thin fin structure on the buried oxide layer, wherein the thin fin structure includes a first hard mask on a semiconductor fin, wherein the semiconductor fin is disposed between the first hard mask and a surface of the buried oxide layer; and a thick mesa structure on the buried oxide layer, and wherein the thick mesa structure includes a semiconductor mesa. The system for fabricating an integrated circuit chip enables: providing a buried oxide layer on and in direct mechanical contact with a semiconductor wafer; and concurrently forming at least one fin-type field effect transistor and at least one thick-body device on the buried oxide layer. | 05-28-2009 |
| 20090305471 | THIN SILICON SINGLE DIFFUSION FIELD EFFECT TRANSISTOR FOR ENHANCED DRIVE PERFORMANCE WITH STRESS FILM LINERS - The present invention provides a semiconducting device structure including a thin SOI region, wherein the SOI device is formed with an optional single thin diffusion, i.e., offset, spacer and a single diffusion implant. The device silicon thickness is thin enough to permit the diffusion implants to abut the buried insulator but thick enough to form a contacting silicide. Stress layer liner films are used both over nFET and pFET device regions to enhance performance. | 12-10-2009 |
David M. Fried, Hopewell Junction, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20110062555 | SEMICONDUCTOR STRUCTURE HAVING VARACTOR WITH PARALLEL DC PATH ADJACENT THERETO - A semiconductor structure includes a semiconductor substrate having a first region of a first polarity and a second region of a second polarity adjacent to the first region; and a first terminal including: a first deep trench located in the first region, a first node dielectric abutting all but an upper portion of sidewalls and a bottom of the first deep trench; a first conductive inner electrode inside the first node dielectric and electrically insulated from the first region by the first node dielectric; and a first electrical contact electrically coupling the first conductive inner electrode to the first region. | 03-17-2011 |
David M. Fried, Brewster, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20080233743 | Method and Structure for Self-Aligned Device Contacts - Disclosed are embodiments of a semiconductor structure with a partially selfaligned contact in lower portion of the contact is enlarged to reduce resistance without impacting device yield. Additionally, the structure optionally incorporates a thick middle-of-the-line (MOL) nitride stress film to enhance carrier mobility. Embodiments of the method of forming the structure comprise forming a sacrificial section in the intended location of the contact. This section is patterned so that it is self-aligned to the gate electrodes and only occupies space that is intended for the future contact. Dielectric layer(s) (e.g., an optional stress layer followed by an interlayer dielectric) may be deposited once the sacrificial section is in place. Conventional contact lithography is used to etch a contact hole through the dielectric layer(s) to the sacrificial section. The sacrificial section is then selectively removed to form a cavity and the contact is formed in the cavity and contact hole. | 09-25-2008 |
| 20080308936 | METHOD AND STURCTURE FOR SELF-ALIGNED DEVICE CONTACTS - Disclosed are embodiments of a semiconductor structure with a partially self-aligned contact in lower portion of the contact is enlarged to reduce resistance without impacting device yield. Additionally, the structure optionally incorporates a thick middle-of-the-line (MOL) nitride stress film to enhance carrier mobility. Embodiments of the method of forming the structure comprise forming a sacrificial section in the intended location of the contact. This section is patterned so that it is self-aligned to the gate electrodes and only occupies space that is intended for the future contact. Dielectric layer(s) (e.g., an optional stress layer followed by an interlayer dielectric) may be deposited once the sacrificial section is in place. Conventional contact lithography is used to etch a contact hole through the dielectric layer(s) to the sacrificial section. The sacrificial section is then selectively removed to form a cavity and the contact is formed in the cavity and contact hole. | 12-18-2008 |
| 20090090974 | DUAL STRESS LINER STRUCTURE HAVING SUBSTANTIALLY PLANAR INTERFACE BETWEEN LINERS AND RELATED METHOD - A dual stress liner structure having a substantially planar interface between liners and a related method are disclosed. In one embodiment, a dual stress liner structure may include a tensile stress liner over an NFET, the NFET including a PFET adjacent thereto; and a compressive stress liner over the PFET, wherein an upper surface of the compressive stress liner is substantially planar with an upper surface of the tensile stress liner at an interface therebetween. | 04-09-2009 |
| 20100283089 | METHOD OF REDUCING STACKING FAULTS THROUGH ANNEALING - Accordingly, in one embodiment of the invention, a method is provided for reducing stacking faults in an epitaxial semiconductor layer. In accordance with such method, a substrate is provided which includes a first single-crystal semiconductor region including a first semiconductor material, the first semiconductor region having a <110> crystal orientation. An epitaxial layer including the first semiconductor material is grown on the first semiconductor region, the epitaxial layer having the <110> crystal orientation. The substrate is then annealed with the epitaxial layer at a temperature greater than 1100 degrees Celsius in an ambient including hydrogen, whereby the step of annealing reduces stacking faults in the epitaxial layer. | 11-11-2010 |
David Michael Fried, Brewster, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20080272398 | CONDUCTIVE SPACERS FOR SEMICONDUCTOR DEVICES AND METHODS OF FORMING - A method of forming a conductive spacer on a semiconductor device. The method includes depositing a polysilicon layer on the semiconductor device, selectively implanting dopant ions in the polysilicon layer on a first side of a transistor region of the semiconductor device to define a conductive spacer area, and removing the polysilicon layer except for the conductive spacer area. Optionally, a silicidation process can be performed on the conductive spacer area so that the conductive spacer is made up of metal silicide. | 11-06-2008 |
| 20080310808 | PHOTONIC WAVEGUIDE STRUCTURE WITH PLANARIZED SIDEWALL CLADDING LAYER - A photonic waveguide structure includes a first photonic waveguide layer located over a substrate. A sidewall cladding layer is located cladding a sidewall, but not covering a top, of the first photonic waveguide layer. A second photonic waveguide layer may be located upon the top of the sidewall cladding layer while contacting, but not straddling, the first photonic waveguide layer. The sidewall cladding layer protects the first photonic waveguide layer from environmental exposure, thus providing enhanced performance of a photonic waveguide structure. A planarizing sidewall cladding layer allows the fabrication of optical chips with multiple layers of lithographically defined devices. | 12-18-2008 |
David Michael Fried, Hopewell Junction, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20090212388 | HIGH-Z STRUCTURE AND METHOD FOR CO-ALIGNMENT OF MIXED OPTICAL AND ELECTRON BEAM LITHOGRAPHIC FABRICATION LEVELS - A structure for aligning a first set of features of a fabrication level of an integrated circuit chip to an electron beam alignment target. The structure including a first trench in a semiconductor substrate, the first trench extending from a top surface of the substrate into the substrate a first distance; an electron back-scattering layer in a bottom of the first trench; a dielectric capping layer in the trench over the back-scattering layer; and a second trench in the substrate, the second trench extending from the top surface of the substrate into the substrate a second distance, the second distance less than the first distance. | 08-27-2009 |
Wayne Fried, Maspeth, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20110067601 | PRODUCTION OF CEMENT ADDITIVES FROM COMBUSTION PRODUCTS OF HYDROCARBON FUELS AND STRENGTH ENHANCING METAL OXIDES - The present invention provides combustion products of hydrocarbon fuels and controlled amounts of metal oxide strength enhancing materials. The combustion products are useful as additives to cementitious materials. A hydrocarbon fuel such as coal is introduced into a combustion chamber and selected amounts of materials comprising CaO, SiO | 03-24-2011 |