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Frey, FR
Alexandre Frey, Paris FR
| Patent application number | Description | Published |
|---|---|---|
| 20080320315 | Method for Creating a Secure Counter on an On-Board Computer System Comprising a Chip Card - According to the inventive method, the chip card, a counting function (FC), a counter (Cpt) and a private key (Cf) stored in the write-only part of the memory region are stored in a persistent memory, the counter and the private key (Cf) being accessible only by the counting function (FC). When the chip card receives a counter request emitted by an requesting entity (ER), the counting function (FC) performs a modification of the counter (Cpt) and a calculation of a signature, and sends a response to the applicant entity (ER). When the on-board system receives the response to the counter request, the signature contained in the response is checked. | 12-25-2008 |
| 20090165148 | METHOD FOR AUTHENTICATING APPLICATIONS OF A COMPUTER SYSTEM - The invention relates to a method for authenticating applications of a computer system including: a microprocessor, a plurality of applications, a general operating system (OS2) which can execute and manage the applications and which can associate each application identifier ( | 06-25-2009 |
Alexandre Frey, Meudon FR
| Patent application number | Description | Published |
|---|---|---|
| 20110162083 | SYSTEM AND METHOD FOR SECURING DATA - The invention relates to a system and method for making data secure. The inventive system is characterized in that it comprises:—a monotonic counter;—a computational entity;—a physical data medium comprising one or a plurality of data blocks, a first master block comprising the last value recovered from the monotonic counter, an identifier of the last data block written on said medium, a first authentication code guaranteeing the authenticity of the written data block or blocks, a second authentication code calculated from the last written data block, said data being fixed at a neutral value, and a third authentication code guaranteeing the authenticity of the first master block, and a second master block forming a replica of the first master block; and—an authentication key. The invention is used, in particular, to make data secure against playback and sudden interruptions in service in embedded systems. | 06-30-2011 |
Christophe Frey, Meylan FR
| Patent application number | Description | Published |
|---|---|---|
| 20090045677 | Power control circuitry and method - A power control circuitry and method of operation are provided for controlling the connection of a voltage source to an associated circuit when that circuit is to enter an active state of operation. The associated circuit has a plurality of circuit portions, and each circuit portion has at least one voltage line for connection to the voltage source. The power control circuitry comprises a series of power switching circuits, each power switching circuit being associated with one of the circuit portions and being provided with an enable signal. Each power switching circuit is responsive to its enable signal being set to connect the voltage source to the at least one voltage line of the associated circuit portion. Further, at least one enable qualifying circuit is provided, each such enable qualifying circuit being associated with one of the power switching circuits and being arranged to generate an output signal used to determine the enable signal provided to a later power switching circuit in the series. Each enable qualifying circuit sets its output signal when both the enable signal provided to the associated power switching circuit is set and the at least one voltage line of the circuit portion associated with that power switching circuit has reached a predetermined voltage level. Such an approach provides a simple and effective mechanism for reducing inrush current in a manner which is independent of process variations. | 02-19-2009 |
Christophe Denis Frey, Meylan FR
| Patent application number | Description | Published |
|---|---|---|
| 20090135663 | Memory device and method of operating such a memory device - A memory device and method of operation are provided. The memory device comprises a plurality of memory cells arranged in at least one column, during a write operation a data value being written to an addressed memory cell within a selected column from said at least one column. A supply voltage line is associated with each column, the supply voltage line being connectable to a first voltage source to provide a supply voltage at a first voltage level to the associated column. Threshold circuitry is connected to a second voltage source having a second voltage level, the threshold circuitry having a threshold voltage. Control circuitry is used during the write operation to disconnect the supply voltage line for the selected column from the first voltage source, and to connect the threshold circuitry to the supply voltage line for the selected column. As a result, the supply voltage to the addressed memory cell transitions to an intermediate voltage level determined by the threshold voltage of the threshold circuitry, thereby de-stabilising the addressed memory cell and assisting in the write operation. The technique of the present invention provides a particularly simple and power efficient technique for implementing a write assist mechanism. | 05-28-2009 |
Christophe Denis Lucien Frey, Meylan FR
| Patent application number | Description | Published |
|---|---|---|
| 20090183032 | Data processing apparatus and method for testing stability of memory cells in a memory device - A data processing apparatus and method are provided for testing stability of memory cells in a memory device. A data processing apparatus comprises a memory device having an array of memory cells for storing data values. Test circuitry is employed in a test mode of operation to execute one or more test patterns in order to detect any memory cells which may malfunction in a normal mode of operation due to cell instability following a write operation, as for example may be caused by body region history effect in embodiments where each memory cell comprises at least one transistor having a body region insulated from a substrate. Each test pattern causes a sequence of access requests to be issued to the memory device whose timing is controlled by a test mode clock signal. Dummy read control circuitry is employed in the test mode of operation, and is responsive at least to each write access request to generate an internal clock signal which has an increased frequency with respect to the test mode clock signal. Further, the dummy read control circuitry is responsive to each write access request to perform using the internal clock signal a write operation to at least one memory cell based on a memory address specified by the write access request, followed by a dummy read operation to the same at least one memory cell, the dummy read operation serving to stress the at least one memory cell with respect to cell stability. This approach provides a very reliable, effective and realistic (in terms of test time) mechanism for detecting memory cells which may malfunction in normal use due to cell instability following a write operation. | 07-16-2009 |
| 20100103747 | Memory device and method of operating such a memory device - A memory device and method of operating such a device are provided. The memory device has a plurality of sub-arrays arranged to form at least one sub-array column having a first end and a second end, with each sub-array comprising a plurality of memory cells arranged in a plurality of memory cell rows and at least one memory cell column. Sub-array access circuitry is associated with each sub-array, for detecting read data from a selected memory cell column of the associated sub-array during a read operation, and global access circuitry then interfaces with the first end of the sub-array column. Each sub-array access circuitry comprises propagation circuitry for producing an output read data value, the propagation circuitry having a first input for receiving the read data detected from the associated sub-array during a read operation and a second input for receiving an output read data value produced by a linked sub-array access circuitry associated with a sub-array nearer the second end of the sub-array column. The propagation circuitry receives a control signal for identifying which of its first or second inputs should be used to produce the output read data value. As a result, an output read data value produced by any sub-array access circuitry is propagated to the global access circuitry via any linked sub-array access circuitry in the sub-array column between that sub-array access circuitry and the global access circuitry. This provides a particularly simple technique for propagating the read data value to the global access circuitry, which has both predictable timing, and consumes low power. | 04-29-2010 |
| 20100246278 | Accessing data within a memory formed of memory banks - A memory is disclosed that comprises: an input for receiving an input signal and an output for outputting data; a plurality of data storage cells for storing individual units of data; said plurality of data storage cells being arranged in an array; a plurality of said arrays; each of said arrays comprising detecting circuitry for detecting and outputting stored data in response to a control signal received at said detecting circuitry; delay circuitry for providing a delay to said control signal sent to said detecting circuitry of at least some of said plurality of arrays, said delay provided to said control signal being longer for at least one array located closer to an input and output of said memory than it is to at least one array located further from an input and output of said memory. | 09-30-2010 |
| 20110051487 | Read only memory cell for storing a multiple bit value - A read only memory cell for storing a multiple bit value is disclosed. The read only memory cell comprises: at least three output lines, each of the at least three output lines representing a different multiple bit value; a switching device connected between a single one of the three output lines and a voltage source. The switching device provides an electrical connection between the voltage source and the single one of the three output lines in response to a switching signal, a voltage of the connected output line switching value in response to connection to the predetermined voltage and the multiple bit value represented by the output line is thereby selected. There is also an output device provided for outputting the selected multiple bit value. | 03-03-2011 |
Laurent Frey, Fontaine FR
| Patent application number | Description | Published |
|---|---|---|
| 20080197285 | Ultrasensitive Optical Detector Having a Large Temporal Resolution and Using a Waveguide, and Methods For Producing Said Detector - Ultrasensitive optical detector with high resolution in time, using a waveguide, and processes for manufacturing this detector | 08-21-2008 |
| 20080272302 | Ultra-Sensitive Optical Detector With High Time Resolution - An ultra-sensitive optical detector with large time resolution, using a surface plasmon. The optical detector is configured to detect at least one photon, and including a dielectric substrate, and on the substrate, at least one bolometric detection component, that generates an electrical signal from the energy of received photon(s). Additionally, at least one coupling component is formed on the substrate, distinct from the detection component and including a metal component, and generates a surface plasmon by interaction with the photon(s) and guiding the plasmon right up to the detection component, which then absorbs the energy of the surface plasmon. | 11-06-2008 |
| 20090020701 | HIGH TIME-RESOLUTION ULTRASENSITIVE OPTICAL DETECTOR, USING GRATING COUPLING - This detector is intended to detect at least one photon and comprises a dielectric substrate ( | 01-22-2009 |
| 20090127460 | HIGH TIME-RESOLUTION ULTRASENSITIVE OPTICAL SENSOR USING A PLANAR WAVEGUIDE LEAKAGE MODE, AND METHODS FOR MAKING SAME - A high time-resolution ultrasensitive optical detector, using a planar waveguide leakage mode, and methods for making the detector. The detector includes a stacking with a dielectric substrate, a detection element, first and second dielectric layers, and a dielectric superstrate configured to send photon(s) into the light guide formed by the first layer. The thicknesses of the layers is chosen to enable a resonant coupling between the photon(s) and a leakage mode of the guide, the stacking having an absorption resonance linked to the leakage mode for a given polarization of the photon(s). | 05-21-2009 |
Michel Frey, Paris FR
| Patent application number | Description | Published |
|---|---|---|
| 20090196943 | Preventing/Treating signs of skin stress/aging by bioenergetically modifying acupuncture points of the face or neck - A regime or regimen for preventing and/or treating the signs of aging and/or stress of the skin, especially for (i) smoothing skin wrinkles and/or relaxing marks on the forehead and/or (ii) tonifying the cheeks, entails topically applying, advantageously via transdermal delivery, onto at least one acupuncture point of the face or the neck of an individual in need of such treatment, notably the acupuncture points PC-1, 6-E, 18-IG, 19-GI, 23-VC, or a restricted area of the face or the neck containing same, at least one bioactive agent modifying the bioenergetic environment at said at least one acupuncture application point and thus mimicking the effects of acupuncture, for example a relaxing/tonifying essential oil. | 08-06-2009 |
Nicolas Frey, Mulhouse FR
| Patent application number | Description | Published |
|---|---|---|
| 20100280986 | SYSTEMS AND METHODS FOR TAILORING ACUTE AND CHRONIC VIRAL INFECTION TREATMENTS TO INCREASE THE PROBABILITY OF "CURE" FOR A GIVEN SUBJECT - In various embodiments, systems and methods are provided for increasing the likelihood of a sustained virological response or “cure” using a model of patient physiology incorporating a subjects race, gender, age, weight, concomitant medicines and disease state, immune response status, and responsiveness to drug therapies to simultaneously characterize the change in viral burden in the subject in terms of velocity of viral load decline. In an embodiment, once viral load in a subject is below a physical measurement limit, the model can extrapolate the subject's observed viral velocity toward a physiological target shown to be highly correlated with “cure.” In further embodiments, the model can be used for personalized medicine—“the right drug at the right dose for the right treatment duration for the right patient.” Accordingly, the model can provide optimal value for treatment and reducing the high cost of side effects. | 11-04-2010 |
Pierre-Régis Frey, Lutterbach FR
| Patent application number | Description | Published |
|---|---|---|
| 20110272845 | PROCESS FOR MANUFACTURING A LOOPED MATERIAL BAND - A process of manufacturing a looped material band for use as a conveyor belt, a conveyor, a transmission belt or the like in which the ends of the band are assembled by fitting together two serrations that have complementary shapes and are connected by at least one transverse locking rod that is inserted through transverse openings arranged in the teeth of the serrations. The process comprises the steps of producing the transverse openings by machining the ends of the band to remove material in an area corresponding at least to the transverse openings to be produced, placing a transverse core pin in each machined area, overmolding material in the machined areas to restore the ends of the band, and one removing, after polymerization of the material, the transverse core pins that form the transverse openings. | 11-10-2011 |
Vincent Frey, Cesson-Sevigne FR
| Patent application number | Description | Published |
|---|---|---|
| 20100180320 | ACCESS MANAGEMENT METHOD - The invention relates to a data transmission system that includes the step of a first user or at least one second user accessing a resource. The novel feature of the invention is the fact that access to said resource is inhibited as long as said first and second users have not requested access thereto. | 07-15-2010 |