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Freking, MN
Anthony J. Freking, White Bear Lake, MN US
| Patent application number | Description | Published |
|---|---|---|
| 20090074976 | METHOD OF REDUCING MOTTLE AND STREAK DEFECTS IN COATINGS - The invention provides methods of reducing visible defects in curable coating compositions. In one embodiment, the method includes coating a curable composition onto a substrate, removing solvent from the curable composition, and heating the dried curable composition to a temperature at which the curable coating exhibits leveling flow. In another embodiment, the curable composition is coated onto a substrate, and then is heated to a temperature at which the curable coating exhibits leveling flow. | 03-19-2009 |
Anthony J. Freking, Vadnais Heights, MN US
| Patent application number | Description | Published |
|---|---|---|
| 20080266501 | ADHESIVE STACKING FOR MULTIPLE OPTICAL FILMS - In a new packaging method for light management films in displays, such as liquid crystal displays, a stack of two or more optical films is held together before insertion into the display frame. The stack includes at least two of the films that are adhered together using adhesive positioned outside the viewing area of the films. In some embodiments, the adhesive is provided at one or more tabs provided around the periphery of the film stack. | 10-30-2008 |
Ronald E. Freking, Rochester, MN US
| Patent application number | Description | Published |
|---|---|---|
| 20080307146 | STRUCTURE FOR DYNAMICALLY SCALABLE QUEUES FOR PERFORMANCE DRIVEN PCI EXPRESS MEMORY TRAFFIC - A method, computer system, and PCI Express device/protocol for a design structure that enables high performance IO data transfers for multiple, different IO configurations, which include variable packet sizes and/or variable/different numbers of transactions on the IO link. PCI Express protocol is enhanced to support utilization of counters and dynamically variable queue sizes. In addition to the standard queue entries, several (or a selected number of) dynamically changeable queue entries are provided/reserved and a dynamic queue modification (DQM) utility is provided within the enhanced PCI Express protocol to monitor ongoing, current data transfer and manage when the size(s) of the queue entries are modified (increased or decreased) based on current data traffic transmitting on the PCI Express IO link. The enhanced PCI Express protocol provides an equilibrium point at which many large data packets are transferred efficiently, while imposing a limit on the number of each size of packets outstanding. | 12-11-2008 |
| 20080313240 | Method for Creating Data Transfer Packets With Embedded Management Information - In a method of communicating management information from a completing entity to a requesting entity in a digital communication system, the availability of management information to be sent from the completing entity to the requesting entity is detected when generating a data packet that does not have a primary purpose of transmitting management information. The management information is included in a management information data field and the management information data field is appended to the data packet. The data packet and the management information are transmitted from the completing entity to the requesting entity. | 12-18-2008 |
| 20090094385 | Techniques for Handling Commands in an Ordered Command Stream - A technique for handling commands includes assigning respective first tags to ordered commands included in an ordered command stream. Respective second tags are then assigned to subsequent commands that follow an initial command (included in the ordered commands). Each of the respective second tags correspond to one the respective first tags that is associated with an immediate previous one of the ordered commands. The initial command is sent to an execution engine in a first cycle. At least one of the subsequent commands is sent to the execution engine prior to completion of execution of the initial command. | 04-09-2009 |
| 20090125666 | DYNAMICALLY SCALABLE QUEUES FOR PERFORMANCE DRIVEN PCI EXPRESS MEMORY TRAFFIC - A computer program product for implementing a method within a data processing system and a PCI Express protocol for enabling high performance IO data transfers for multiple, different IO configurations, which include variable packet sizes and/or variable/different numbers of transactions on the IO link. PCI Express protocol is enhanced to support utilization of counters and dynamically variable queue sizes. In addition to the standard queue entries, several (or a selected number of) dynamically changeable queue entries are provided/reserved and a dynamic queue modification (DQM) utility is provided within the enhanced PCI Express protocol to monitor ongoing, current data transfer and manage when the size(s) of the queue entries are modified (increased or decreased) based on current data traffic transmitting on the PCI Express IO link. The enhanced PCI Express protocol provides an equilibrium point at which many large data packets are transferred efficiently, while imposing a limit on the number of each size of packets outstanding. | 05-14-2009 |
Ronald Ernest Freking, Rochester, MN US
| Patent application number | Description | Published |
|---|---|---|
| 20090132876 | Maintaining Error Statistics Concurrently Across Multiple Memory Ranks - A method and apparatus to maintain memory read error information concurrently across multiple ranks in a computer memory. An error detection unit associates a read error with a particular rank and with a particular chip in the rank. The error detection unit reports the error and the associated rank ID and chip ID to an error logging unit. The error logging unit maintains, for each rank ID and chip ID for which an error has been detected, a total number of errors that occur. A memory controller uses a fault pattern in the error logging unit to replace failing memory chips or memory ranks with a spare memory chip or a spare memory rank. | 05-21-2009 |
| 20090157972 | Hash Optimization System and Method - A computer implemented method, apparatus and program product automatically optimizes hash function operation by recognizing when a first hash function results in an unacceptable number of cache misses, and by dynamically trying another hash function to determine which hash function results in the most cache hits. In this manner, hardware optimizes hash function operation in the face of changing loads and associated data flow patterns. | 06-18-2009 |
| 20110119439 | Spacing Periodic Commands to a Volatile Memory for Increased Performance and Decreased Collision - A periodic command spacing mechanism is provided for spacing periodic commands (e.g., refresh commands, ZQ calibration, etc.) to a volatile memory (e.g., SDRAM, DRAM, EDRAM, etc.) for increased performance and decreased collision. In one embodiment, periodic command requests are monitored and if a collision is detected between two or more of the requests, the colliding requests are spaced with respect to one another by a timer offset applied on a chip select basis. The periodic command spacing mechanism may be used in conjunction with command arbitration to make sure the periodic commands are executed without significantly impacting performance (e.g., Reads and Writes are allowed to flow). Preferably, the periodic command requests are initialized by generating an initial sequence of individual requests, each successive request in the initial sequence being generated spaced apart with respect to the previous request by a timer offset applied on a chip select basis. | 05-19-2011 |