| Patent application number | Description | Published |
|---|
| 20080290399 | Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region - A nonvolatile charge trap memory device is described. The device includes a substrate having a channel region and a pair of source/drain regions. A gate stack is above the substrate over the channel region and between the pair of source/drain regions. The gate stack includes a multi-layer charge-trapping region having a first deuterated layer. The multi-layer charge-trapping region may further include a deuterium-free charge-trapping layer. | 11-27-2008 |
| 20080290400 | SONOS ONO stack scaling - Scaling a nonvolatile trapped-charge memory device and the article made thereby. In an embodiment, scaling includes multiple oxidation and nitridation operations to provide a tunneling layer with a dielectric constant higher than that of a pure silicon dioxide tunneling layer but with a fewer hydrogen and nitrogen traps than a tunneling layer having nitrogen at the substrate interface. In an embodiment, scaling includes forming a charge trapping layer with a non-homogenous oxynitride stoichiometry. In one embodiment the charge trapping layer includes a silicon-rich, oxygen-rich layer and a silicon-rich, oxygen-lean oxynitride layer on the silicon-rich, oxygen-rich layer. In an embodiment, the method for scaling includes a dilute wet oxidation to density a deposited blocking oxide and to oxidize a portion of the silicon-rich, oxygen-lean oxynitride layer. | 11-27-2008 |
| 20080291732 | Three cycle SONOS programming - A method to eliminate over-erase in a nonvolatile trapped-charge memory array during write operations includes a three-cycle process of bulk programming the memory array, bulk erasing the memory array and selectively inhibiting one or more memory cells in the memory array while applying a programming voltage to the memory array. | 11-27-2008 |
| 20080293207 | INTEGRATION OF NON-VOLATILE CHARGE TRAP MEMORY DEVICES AND LOGIC CMOS DEVICES - A semiconductor structure and method to form the same. The semiconductor structure includes a substrate having a non-volatile charge trap memory device disposed on a first region and a logic device disposed on a second region. A charge trap dielectric stack may be formed subsequent to forming wells and channels of the logic device. HF pre-cleans and SC1 cleans may be avoided to improve the quality of a blocking layer of the non-volatile charge trap memory device. The blocking layer may be thermally reoxidized or nitridized during a thermal oxidation or nitridation of a logic MOS gate insulator layer to densify the blocking layer. A multi-layered liner may be utilized to first offset a source and drain implant in a high voltage logic device and also block silicidation of the nonvolatile charge trap memory device. | 11-27-2008 |
| 20080296664 | INTEGRATION OF NON-VOLATILE CHARGE TRAP MEMORY DEVICES AND LOGIC CMOS DEVICES - A semiconductor structure and method to form the same. The semiconductor structure includes a substrate having a non-volatile charge trap memory device disposed on a first region and a logic device disposed on a second region. A charge trap dielectric stack may be formed subsequent to forming wells and channels of the logic device. HF pre-cleans and SC1 cleans may be avoided to improve the quality of a blocking layer of the non-volatile charge trap memory device. The blocking layer may be thermally reoxidized or nitridized during a thermal oxidation or nitridation of a logic MOS gate insulator layer to densify the blocking layer. A multi-layered liner may be utilized to first offset a source and drain implant in a high voltage logic device and also block silicidation of the nonvolatile charge trap memory device. | 12-04-2008 |
| 20090032863 | Nitridation oxidation of tunneling layer for improved SONOS speed and retention - A method for forming a tunneling layer of a nonvolatile trapped-charge memory device and the article made thereby. The method includes multiple oxidation and nitridation operations to provide a dielectric constant higher than that of a pure silicon dioxide tunneling layer but with a fewer hydrogen and nitrogen traps than a tunneling layer having nitrogen at the substrate interface. The method provides for an improved memory window in a SONOS-type device. In one embodiment, the method includes an oxidation, a nitridation, a reoxidation and a renitridation. In one implementation, the first oxidation is performed with O | 02-05-2009 |
| 20090080246 | Method and apparatus for reduction of bit-line disturb and soft-erase in a trapped-charge memory - A method and device for trading off inhibit disturb against bit-line disturb in a non-volatile memory where a threshold shift per inhibit disturb is increased, a threshold shift per bit-line disturb is decreased and the total threshold shift over the expected lifetime of the non-volatile memory due to inhibit disturbs is approximately equalized with the total threshold shift over the expected lifetime of the non-volatile memory due to bit-line disturbs. | 03-26-2009 |
| 20090086538 | METHOD AND APPARATUS FOR PROGRAMMING MEMORY CELL ARRAY - Disclosed are a method and device for programming an array of memory cells. | 04-02-2009 |
