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Frederick, Jr.
Billy J. Frederick, Jr., Woodbury, MN US
| Patent application number | Description | Published |
|---|---|---|
| 20090123754 | MICROSPHERES HAVING A HIGH INDEX OF REFRACTION - The present disclosure relates to microspheres (i.e., beads) having a high index of refraction. The disclosure also relates to retroreflective articles, and in particular pavement markings, comprising such microspheres. | 05-14-2009 |
Marlin Frederick, Jr., Cedar Park, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20090033394 | Data retention in operational and sleep modes - A circuit is disclosed for retaining a signal value during a sleep mode while a portion of said circuit is powered down comprising: a clock signal input operable to receive a clock signal; at least one latch clocked by said clock signal; a data input, a data output and a forward data path therebetween, wherein a signal value is operable to be received at said data input, is clocked through said at least one latch and passes to said data output along said forward data path; at least one of said at least one latch comprises a retention latch operable to retain a signal value during said sleep mode, said retention latch not being located on said forward data path; and a tristateable device, said tristateable device being arranged between said forward data path and said retention latch and being operable to selectively isolate said retention latch from said forward data path in response to receipt of a first sleep signal; wherein in response to receipt of a second sleep signal, said second sleep signal being received after said first sleep signal, said circuit is operable to enter said sleep mode such that a voltage difference across said portion of said circuit is reduced such that said portion of said circuit is powered down, and a voltage difference across said retention latch and said tristateable device is maintained. | 02-05-2009 |
| 20090207552 | Decoupling capacitors - A decoupling capacitor is disclosed that has an n-type portion and a p-type portion in a semiconductor, said decoupling capacitor comprising an NFET transistor and a PFET transistor, said PFET transistor being substantially formed in said n-type portion and said NFET transistor being substantially formed in said p-type portion, a boundary between said n-type portion and said p-type portion being substantially straight, said transistors being arranged such that a source and drain of said PFET transistor are connected to a high voltage rail and a source and drain of said NFET transistor are connected to a low voltage rail. | 08-20-2009 |
Marlin Wayne Frederick, Jr., Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20110121876 | State retention circuit and method of operation of such a circuit - A state retention circuit is provided comprising a pulse generator which is configured in a non-retention mode of operation to be responsive to a clock signal to periodically assert a pulse, and a storage structure that comprises a storage element for storing state and an isolation structure for responding to the asserted pulse. In particular, the isolation structure is responsive to the asserted pulse to cause the storage element to update its stored state dependent on an input to the storage structure. Conversely, in the absence of the asserted pulse, the isolation structure isolates the storage element from the input. The pulse generator can be driven by a retention control signal to enter a retention mode of operation, during which it does not assert the pulse irrespective of changes in the clock signal. As a result, the isolation structure isolates the storage element from the input during the retention mode of operation, causing the storage element to retain its stored state prior to entry of the retention mode of operation irrespective of changes in the clock signal or changes in the input during the retention mode of operation. Such a design provides a clock independent pulse retention storage structure of small area, high performance and low energy consumption. | 05-26-2011 |
Norman Frederick, Jr., Vista, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100084751 | Double Broken Seal Ring - The amount of signal propagation and moisture penetration and corresponding reliability problems due to moisture penetration degradation in an IC can be reduced by fabricating two seal rings with non-adjacent gaps. In one embodiment, the same effect can be achieved by fabricating a wide seal ring with a channel having offset ingress and egress portions. Either of these embodiments can also have grounded seal ring segments which further reduce signal propagation. | 04-08-2010 |
| 20100291888 | MULTI-MODE MULTI-BAND POWER AMPLIFIER MODULE - A multi-mode multi-band power amplifier (PA) module is described. In an exemplary design, the PA module includes multiple power amplifiers, multiple matching circuits, and a set of switches. Each power amplifier provides power amplification for its input signal when selected. Each matching circuit provides impedance matching and filtering for its power amplifier and provides a respective output signal. The switches configure the power amplifiers to support multiple modes, with each mode being for a particular radio technology. Each power amplifier supports at least two modes. The PA module may further include a driver amplifier and an additional matching circuit. The driver amplifier amplifies an input signal and provides an amplified signal to the power amplifiers. The additional matching circuit combines the outputs of other matching circuits and provides an output signal with higher output power. The driver amplifier and the power amplifiers can support multiple output power levels. | 11-18-2010 |
Norman L. Frederick, Jr., Vista, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100327976 | INTEGRATED POWER AMPLIFIER WITH LOAD INDUCTOR LOCATED UNDER IC DIE - A compact integrated power amplifier is described herein. In an exemplary design, an apparatus includes (i) an integrated circuit (IC) die having at least one transistor for a power amplifier and (ii) an IC package having a load inductor for the power amplifier. The IC die is mounted on the IC package with the transistor(s) located over the load inductor. In an exemplary design, the IC die includes a transistor manifold that is placed over the load inductor on the IC package. The transistor(s) are fabricated in the transistor manifold, have a drain connection in the center of the transistor manifold, and have source connections on two sides of the transistor manifold. The IC die and the IC package may include one or more additional power amplifiers. The transistor(s) for each power amplifier may be located over the load inductor for that power amplifier. | 12-30-2010 |