| Patent application number | Description | Published |
|---|
| 20090050973 | INTEGRATED CIRCUIT INCLUDING A FIRST CHANNEL AND A SECOND CHANNEL - An integrated circuit is disclosed. In one embodiment, the integrated circuit includes a first area and a second area. The first area is stress engineered to provide enhanced mobility in a first channel that has a first width. The second area is stress engineered to provide enhanced mobility in a second channel that has a second width. The first channel and the second channel provide a combined current that is greater than a single current provided via a single channel having a single width that is substantially equal to the sum of the first width and the second width. | 02-26-2009 |
| 20090128383 | Compensation of nonlinearity of single ended Digital to analog converters - This disclosure relates to a compensating for nonlinearity resulting from a capacitance feedback in current cells of a single ended digital to analog circuit. | 05-21-2009 |
| 20090147542 | Systems and methods for driving a transistor - This disclosure relates to monitoring and controlling a voltage characteristic of a Drain Extended Metal Oxide Semiconductor (DeMOS) transistor. | 06-11-2009 |
| 20090250763 | INTEGRATED CIRCUIT INCLUDING A FIRST CHANNEL AND A SECOND CHANNEL - An integrated circuit is disclosed. In one embodiment, the integrated circuit includes a first area and a second area. The first area is stress engineered to provide enhanced mobility in a first channel that has a first width. The second area is stress engineered to provide enhanced mobility in a second channel that has a second width. The first channel and the second channel provide a combined current that is greater than a single current provided via a single channel having a single width that is substantially equal to the sum of the first width and the second width. | 10-08-2009 |
| 20100111222 | Digital Modulation Jitter Compensation for Polar Transmitter - This disclosure relates to clock jitter suppression in digital to analog converter generated pulses for a polar transmitter. | 05-06-2010 |
| 20100141327 | COMPENSATION OF NONLINEARITY OF SINGLE ENDED DIGITAL TO ANALOG CONVERTERS - This disclosure relates to a compensating for nonlinearity resulting from a capacitance feedback in current cells of a single ended digital to analog circuit. | 06-10-2010 |
| 20110037499 | COMPARATOR FOR TECHNOLOGIES WITH TRANSIENT VARIATIONS OF TRANSISTOR PARAMETERS - This disclosure relates to permuting transistors to compensate for offsets generated by transient variations of the transistors' parameters. | 02-17-2011 |
| 20110043293 | DeMOS VCO - The present disclosure relates voltage controlled oscillators (VCO) and digitally controlled oscillators (DCO). In one implementation, a VCO is implemented with drain extended MOS transistors (DeMOS). In another implementation, a DCO is implemented with DeMOS devices. | 02-24-2011 |
| 20110043294 | DeMOS DCO - The present disclosure relates voltage controlled oscillators (VCO) and digitally controlled oscillators (DCO). In one implementation, a VCO is implemented with drain extended MOS transistors (DeMOS). In another implementation, a DCO is implemented with DeMOS devices. | 02-24-2011 |
| 20110085616 | DIGITAL TO ANALOG CONVERTER COMPRISING MIXER - In some embodiments, digital to analog converters are provided which comprise a plurality of cells. Each cell comprises a mixer and coupling circuitry to selectively couple a local oscillator signal to said mixer. | 04-14-2011 |
