| Patent application number | Description | Published |
|---|
| 20080217732 | Carbon memory - An integrated circuit including a memory cell and methods of manufacturing the integrated circuit are described. The memory cell includes a resistive memory element including a top contact, a bottom contact, and a carbon storage layer disposed between the top contact and the bottom contact. The memory cell operates at a voltage in a range of approximately 0.5V to approximately 3V, and at a current in a range of approximately 1 μA to approximately 150 μA. | 09-11-2008 |
| 20080296559 | Method for Fabricating a Nanoelement Field Effect Transistor with Surrounded Gate Structure - A nanoelement field effect transistor includes a nanotube disposed on the substrate. A first source/drain region is coupled to a first end portion of the nanoelement and a second source/drain region is coupled to a second end portion of the nanoelement. A recess in a surface region of the substrate is arranged in such a manner that a region of the nanoelement arranged between the first and second end portions is taken out over the entire periphery of the nanoelement. A gate-insulating structure covers the periphery of the nanoelement and a gate structure covers the periphery of the gate-insulating structure. | 12-04-2008 |
| 20090026524 | Stacked Circuits - An integrated circuit includes a first integrated circuit layer including at least one first transistor channel region and having a wafer bonding interface. The integrated circuit may further include at least one second integrated circuit layer including at least one second transistor channel region and being arranged at the wafer bonding interface of the first integrated circuit layer. | 01-29-2009 |
| 20090046499 | INTEGRATED CIRCUIT INCLUDING MEMORY HAVING LIMITED READ - An integrated circuit including a memory with an array of memory cells, each memory cell comprising a non-volatile memory element; and a limited read circuit communicatively coupled to the array of memory cells. | 02-19-2009 |
| 20090201715 | Carbon Diode Array for Resistivity Changing Memories - An integrated circuit and method for manufacturing an integrated circuit are described. In one embodiment, the integrated circuit includes a memory cell including a resistivity changing memory element and a carbon diode electrically coupled to the resistivity changing memory element. | 08-13-2009 |
| 20090213830 | COMMUNICATION SYSTEM - A communication system is disclosed. In one embodiment, the communication system includes a communication device set up to execute a process, configured to put itself into an activated state or into a deactivated state at alternate times, receive time information in a first operating state of the activated state, take the received time information as a basis for ascertaining the later time at which useful information is transmitted to the communication device, receive the useful information at the later time in a second operating state of the activated state. Individual components of the communication device are able to be put into an activated state or into a deactivated state independently of one another. | 08-27-2009 |
| 20090321860 | INTEGRATED CIRCUIT HAVING A MAGNETIC TUNNEL JUNCTION DEVICE AND METHOD - An integrated circuit having a magnetic tunnel junction and method. One embodiment provides an integrated circuit having a magnetic tunnel junction is provided. The magnetic tunnel junction includes a barrier layer. The barrier layer includes carbon, pyrolytic carbon, or graphene, or graphite. | 12-31-2009 |
| 20090322319 | MAGNETORESISTIVE SENSOR WITH TUNNEL BARRIER AND METHOD - Magnetoresistive sensors with tunnel barrier and method. One embodiment provides a magnetoresistive sensor having a magnetic tunnel junction is provided. The magnetic tunnel junction includes a barrier layer. The barrier layer includes carbon, pyrolytic carbon, or graphene, or graphite. | 12-31-2009 |
| 20100057685 | INFORMATION STORAGE AND RETRIEVAL SYSTEM - An information storage and retrieval system includes a first data structure and a second data structure. The first data structure is configured to store documents. Each document includes a plurality of data portions. The second data structure is configured to store addresses to each document and data portion stored in the first data structure at addresses defined by an identity of each data portion. | 03-04-2010 |
| 20100061140 | INTEGRATED CIRCUIT INCLUDING DOPED SEMICONDUCTOR LINE HAVING CONDUCTIVE CLADDING - An integrated circuit includes an array of memory cells. Each memory cell includes a diode. The integrated circuit includes a doped semiconductor line formed in a semiconductor substrate. The doped semiconductor line is coupled to a row of diodes. The integrated circuit includes conductive cladding contacting the doped semiconductor line. | 03-11-2010 |
