Patent application number | Description | Published |
20080237684 | Method of manufacturing a nanowire transistor, a nanowire transistor structure, a nanowire transistor field - A method of manufacturing a nanowire transistor includes oxidizing at least a portion of a semiconductor carrier. The semiconductor carrier includes a first carrier portion and a second carrier portion above the first carrier portion. A portion of the oxidized portion is removed, thereby forming an oxide spacer between a portion of the second carrier portion and the first carrier portion. A gate region is formed above at least a portion of the second carrier portion, and a first source/drain region and a second source/drain region are formed. | 10-02-2008 |
20080259687 | Integrated Circuits and Methods of Manufacturing Thereof - Embodiments of the invention relate to integrated circuits having a memory cell arrangement and methods of manufacturing thereof. In one embodiment of the invention, an integrated circuit has a memory cell arrangement which includes a fin structure extending in its longitudinal direction as a first direction, including a first insulating layer, a first active region disposed above the first insulating layer, a second insulating layer disposed above the first active region, a second active region disposed above the second insulating layer, a charge storage layer structure disposed at least next to at least one sidewall of the fin structure covering at least a portion of the first active region and at least a portion of the second active region, and a control gate disposed next to the charge storage layer structure. | 10-23-2008 |
20080308856 | Integrated Circuit Having a Fin Structure - Embodiments of the invention relate generally to a method for manufacturing an integrated circuit, a method for manufacturing a cell arrangement, an integrated circuit, a cell arrangement, and a memory module. In an embodiment of the invention, a method for manufacturing an integrated circuit having a cell arrangement is provided, including forming at least one semiconductor fin structure having an area for a plurality of fin field effect transistors, wherein the area of each fin field effect transistor includes a first region having a first fin structure width, a second region having a second fin structure width, wherein the second fin structure width is smaller than the first fin structure width. Furthermore, a plurality of charge storage regions are formed on or above the second regions of the semiconductor fin structure. | 12-18-2008 |
20090309152 | Integrated Circuits Having a Contact Region and Methods for Manufacturing the Same - In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include a substrate, a fin structure disposed above the substrate, and a memory cell contacting region. The fin structure may include a memory cell region having a plurality of memory cell structures being disposed above one another, each memory cell structure having an active region of a respective memory cell. Furthermore, the memory cell contacting region may be configured to electrically contact each of the memory cell structures, wherein the memory cell contacting region may include a plurality of contact regions, which are at least partially displaced with respect to each other in a direction parallel to the main processing surface of the substrate. | 12-17-2009 |
20100013005 | INTEGRATED CIRCUIT INCLUDING A VERTICAL TRANSISTOR AND METHOD - An integrated circuit including a vertical transistor and method of manufacturing. In one embodiment a vertical transistor is formed in a pillar of a semiconductor substrate. A buried conductive line is separated from the semiconductor substrate by a first insulating layer in a first portion and is electrically coupled to a buried source/drain region of the vertical transistor through a contact structure. A second insulating layer is arranged above and adjacent to the contact structure. At least one of the first and second insulating layers includes a dopant. A doped region is formed in the semiconductor substrate at an interface to the at least one insulating layer. The doped region has a dopant concentration higher than a substrate dopant concentration. | 01-21-2010 |
20100123202 | INTEGRATED CIRCUIT WITH STACKED DEVICES - An integrated circuit with stacked devices. One embodiment provides a surface of a first semiconductor structure of a first crystalline semiconductor material including first and second portions. First structures are formed on the first portions. The second portions remain uncovered. Sacrificial structures of a second, different crystalline material are formed on the second portions. A second semiconductor structure of the first crystalline semiconductor material is formed over the sacrificial structures and over the first structures. | 05-20-2010 |
Patent application number | Description | Published |
20080199974 | Method for Functionalizing Biosensor Chips - A met4hod is disclosed for functionalizing biosensors. The biosensors are based on semiconductor chips mounted on a finished processed wafer. They are provided with sensor fields placed thereupon, which are arranged in any array, and, to be precise, for carrying out a functionalization, for example, with organic molecules such as nucleic acids like DNA, RNA and PNA or with their derivatives, proteins, sugar molecules, or antibodies. | 08-21-2008 |
20080258206 | Self-Aligned Gate Structure, Memory Cell Array, and Methods of Making the Same - A self-aligned gate structure includes a first gate region and a second gate region. The first gate region extends in semiconductor substrate portions to a lesser depth than in isolation trenches that are adjacent to the semiconductor substrate portions. The first gate region comprises a first conductive material. The second gate region is adjacent to the first gate region and extends above a surface of the semiconductor substrate. The second gate region includes a second conductive material. | 10-23-2008 |
20080299722 | Manufacturing method for forming a recessed channel transistor, method for forming a corresponding integrated semiconductor memory device and corresponding self-aligned mask structure - The present invention provides a method for forming a recessed channel transistor comprising the steps of:
| 12-04-2008 |
20090261397 | Integrated Circuit with Floating-Gate Electrodes Including a Transition Metal and Corresponding Manufacturing Method - An integrated circuit is described. The integrated circuit may comprise a multitude of floating-gate electrodes, wherein at least one of the floating-gate electrodes has a lower width and an upper width, the lower width being larger than the upper width, and wherein the at least one of the floating-gate electrodes comprises a transition metal. A corresponding manufacturing method for an integrated circuit is also described. | 10-22-2009 |
20090308741 | Sensor arrangement comprising an electrode for detecting diffused loaded particles - A sensor arrangement for detecting particles potentially contained in an analyte is disclosed. The arrangement includes a substrate; at least one sensor electrode which is arranged on and/or in the substrate and on which scavenger molecules, which hybridize with particles that are potentially contained in an analyte and are to be detected, are immobilized, electrically charged particles generated by hybridization being detectable on the at least one sensor electrode; and at least one diffusion detection electrode which is arranged in a surrounding region of the at least one sensor electrode and is embodied in such a way that it detects electrically charged particles that are generated by hybridization and can be diffused away by the at least one sensor electrode. | 12-17-2009 |
20150214372 | SOI FINFET WITH REDUCED FIN WIDTH DEPENDENCE - The present invention relates to a method for polarizing at least a first finfet transistor and a second finfet transistor, wherein the first finfet transistor has a fin width bigger than the fin width of the second finfet transistor, and both the first finfet transistor and the second finfet transistor have a back gate, and the method comprising applying the same first voltage on the back gate of the first finfet transistor and on the back gate of the second finfet transistor so as to reduce the spread between the off-current value of the first finfet transistor and the off-current value of the second finfet transistor. | 07-30-2015 |
20150357333 | BACK GATE IN SELECT TRANSISTOR FOR EDRAM - This disclosure relates to an eDRAM memory element comprising a first storage node, a bitline node for accessing the value stored in the storage node, and a select transistor, controlling access from the bitline node to the storage node, wherein the select transistor has a front gate and a back gate. | 12-10-2015 |
Patent application number | Description | Published |
20080251833 | Integrated circuits and methods of manufacture - In various embodiments of the invention, integrated circuits and methods of manufacturing integrated circuits are provided. In an embodiment of the invention, an integrated circuit having at least one memory cell is provided. The memory cell includes a dielectric layer disposed above a charge storage region, a word line disposed above the dielectric layer, and a control line disposed at least partially above at least one sidewall of the dielectric layer. | 10-16-2008 |
20090039329 | Integrated Circuit Having a Cell with a Resistivity Changing Layer - In an embodiment of the invention, an integrated circuit having a cell is provided. The cell may include a field effect transistor structure which includes a gate stack and a resistivity changing material structure disposed above the gate stack, wherein the resistivity changing material structure includes a resistivity changing material which is configured to change its resistivity in response to the application of an electrical voltage to the resistivity changing material structure. | 02-12-2009 |
20090097317 | Integrated Circuit Having NAND Memory Cell Strings - Embodiments of the present invention relate generally to integrated circuits and methods for manufacturing an integrated circuit. In an embodiment of the invention, an integrated circuit having a memory cell is provided. The memory cell may include a trench in a carrier, a charge trapping layer structure in the trench, the charge trapping layer structure comprising at least two separate charge trapping regions, electrically conductive material at least partially filled in the trench, and source/drain regions next to the trench. | 04-16-2009 |
20090294895 | INTEGRATED CIRCUIT WITH CONDUCTIVE STRUCTURES - An integrated circuit includes an array of transistors and wordlines, where individual wordlines are coupled to a number of the transistors. Conductive structures that are insulated from the wordlines are disposed in a layer beneath the wordlines and are arranged between the transistors. | 12-03-2009 |