| Patent application number | Description | Published |
|---|
| 20110090747 | INTEGRATED CIRCUIT COMPRISING A NON-DEDICATED TERMINAL FOR RECEIVING AN ERASE PROGRAM HIGH VOLTAGE - The disclosure relates to an integrated circuit electrically powered by a supply voltage and comprising a memory electrically erasable and/or programmable by means of a second voltage greater than the supply voltage. The integrated circuit comprises means for receiving the second voltage by the intermediary of a reception terminal of the supply voltage or by the intermediary of a reception or emission terminal of a data or clock signal. Applicable in particular to electronic tags comprising a reduced number of interconnection terminals. | 04-21-2011 |
| 20110103146 | MEMORY DEVICE OF THE ELECTRICALLY ERASABLE AND PROGRAMMABLE TYPE, HAVING TWO CELLS PER BIT - The memory device includes a memory cell unit of the electrically erasable and programmable non-volatile type including two memory cells respectively connected to two bit lines via two bit line select transistors. The common terminal between the bit line select transistor and the floating-gate transistor of each memory cell of the memory cell unit is connected to the control gate of the floating-gate transistor of the other memory cell of the memory cell unit. | 05-05-2011 |
| 20110141805 | METHOD OF PROGRAMMING AN ELECTRICALLY PROGRAMMABLE AND ERASABLE NON-VOLATILE MEMORY POINT, AND CORRESPONDING MEMORY DEVICE - An electrically programmable and erasable non-volatile memory point may have at least one floating-gate transistor connected to a bit line and to a ground line, and may be programmed with a programming voltage. In an erase phase of the memory point, a first, negative, voltage may be applied to the bit line and to the ground line. The absolute value of the first voltage may be smaller than a threshold value of a PN diode. A second positive voltage which is smaller than the programming voltage may be applied to the control gate of the floating-gate transistor. The difference between the second voltage and the first voltage may be equal to the programming voltage, and, in a writing phase, the first negative voltage may be applied to the control gate of the floating-gate transistor, and the second voltage may be applied to the bit line. | 06-16-2011 |
| 20110181991 | STRUCTURE OF PROTECTION OF AN INTEGRATED CIRCUIT AGAINST ELECTROSTATIC DISCHARGES - An integrated circuit protected against electrostatic discharges, including input/output pads and first and second power supply rails, and: a thyristor forward-connected between each input/output pad and the second rail, each thyristor including, between its anode gate and its anode, a resistor; between each thyristor and the first rail, a diode having its anode connected to the anode gate of the thyristor and having its cathode connected to the first rail via a resistor for adjusting the triggering; and a triggering device capable of conducting a current between the first and second rails when a positive overvoltage occurs between these rails. | 07-28-2011 |
| 20110194219 | INTEGRATED CIRCUIT PROVIDED WITH A PROTECTION AGAINST ELECTROSATATIC DISCHARGES - An integrated circuit protected against electrostatic discharges, having output pads coupled to amplification stages, each stage including, between first and second power supply rails, a P-channel MOS power transistor in series with an N-channel MOS power transistor, this integrated circuit further including protection circuitry for simultaneously turning on the two transistors when a positive overvoltage occurs between the first and second power supply rails. | 08-11-2011 |
| 20120014024 | Method of Testing a Structure Protected from Overvoltages and the Corresponding Structure - An electronic device includes an electronic component and a protection circuit configured to protect the component from overvoltages. A control circuit is configured to inhibit a part of the protection circuit in the presence of a test voltage across terminals of the component. | 01-19-2012 |
| 20120027104 | SINGLE-WIRE BUS COMMUNICATION PROTOCOL - A method for transmitting data over a single-wire bus wherein a first communication channel is defined by pulses of different durations according to the state of the transmitted bit and depending on a reference duration, and a second communication channel is defined by the reference duration. | 02-02-2012 |
| 20120030388 | CONVERSION OF A TWO-WIRE BUS INTO A SINGLE-WIRE BUS - A method of conversion by at least one interface circuit connected between a first bus including at least one data wire and one clock wire, and at least one second single-wire bus, of a transmission between a master circuit connected to the first bus and at least one slave circuit connected to the second bus, wherein a speculative read command is sent to the slave circuit before interpreting the state of a bit for controlling a reading or a writing, originating from the master circuit. | 02-02-2012 |
| 20120030753 | MULTIPROTOCOL COMMUNICATION AUTHENTICATION - A method for authenticating a transmission between a first and a second circuit transiting through at least one third circuit, wherein: data are transmitted from the first to the third circuit, and from the third to the second circuit; a first signature of the data is calculated by the first circuit; at least a second signature of the data is calculated by the third circuit; at least one first portion of the first signature is transmitted by the first circuit to the third one; and the second signature is transmitted by the third circuit to the second one, a portion of this signature being distorted in case of a failure of authentication of the first portion of the first signature by the third circuit. | 02-02-2012 |
